74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear
May 2008
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
Features
n
High speed: f
MAX
=
160MHz (Typ.) at T
A
=
25°C
n
High noise immunity: V
IH
=
2.0V, V
IL
=
0.8V
n
Power down protection is provided on all inputs and
General Description
The VHCT74A is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D INPUT is transferred to the Q OUTPUT during the
positive going transition of the CK pulse. CLR and PR
are independent of the CK and are accomplished by set-
ting the appropriate input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
=
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
outputs
n
Low power dissipation: I
CC
=
2µA (Max.) at T
A
=
25°C
n
Pin and function compatible with 74HCT74
Ordering Information
Order Number
74VHCT74AM
74VHCT74ASJ
74VHCT74AMTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
D
1
, D
2
CK
1
, CK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
Truth Table
Inputs
CLR
L
H
L
H
H
H
Outputs
CK
X
X
X
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
Q
L
H
H
L
H
Q
n
Q
H
L
H
H
L
Q
n
Function
Clear
Preset
No Change
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
2
74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
DC Input Voltage
DC Output Voltage
Note 1
Note 2
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Input Diode Current
Output Diode Current
(3)
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–0.5V to 7.0V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
Input Voltage
Output Voltage
Note 1
Note 2
T
OPR
t
r
, t
f
Operating Temperature
Input Rise and Fall Time
V
CC
=
5.0V ±0.5V
Parameter
Rating
4.5V to +5.5V
0V to +5.5V
0V to V
CC
0V to 5.5V
–40°C to +85°C
0ns/V
∼
20ns/V
Notes:
1. HIGH or LOW state. I
OUT
absolute maximum rating must be observed.
2. V
CC
=
0V.
3. V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active).
4. Unused inputs must be held HIGH or LOW. They may not float.
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
3
74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CC
I
CCT
I
OFF
T
A
=
–40°C
to +85°C
Min.
2.0
2.0
0.8
0.8
0.8
0.8
4.40
3.80
0.1
0.36
±0.1
2.0
1.35
+0.5
0.1
0.44
±1.0
20.0
1.50
+5.0
µA
µA
mA
µA
V
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level Output
Voltage
LOW Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Maximum I
CC
/ Input
Output Leakage
Current (Power
Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
0–5.5
5.5
5.5
0.0
Conditions
Min.
2.0
2.0
Typ.
Max.
Max.
Units
V
V
IN
=
V
IH
I
OH
=
–50µA
or V
IL
I
OH
=
–8mA
V
IN
=
V
IH
I
OL
=
50µA
or V
IL
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
IN
=
3.4V, Other
Inputs
=
V
CC
or GND
V
OUT
=
5.5V
4.40
3.94
4.50
0.0
AC Electrical Characteristics
T
A
=
25°C
Symbol
f
MAX
T
A
=
–40°C
to +85°C
Min.
80
65
7.8
8.8
10.4
11.4
10
1.0
1.0
1.0
1.0
9.0
10.0
12.0
13.0
10
pF
pF
ns
ns
Parameter
Maximum Clock
Frequency
V
CC
(V)
(5)
5.0
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
V
CC
=
Open
(6)
Min.
100
80
Typ.
160
140
5.8
6.3
7.6
8.1
4
24
Max.
Max.
Units
MHz
t
PLH
, t
PHL
Propagation Delay
Time (CK-Q, Q)
t
PLH
, t
PHL
Propagation Delay
Time (CLR, PR-Q, Q)
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Notes:
5. V
CC
is 5.0 ± 0.5V
6. C
PD
is defined as the value of internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(Opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 2 (per flip-flop).
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
4
74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear
AC Operating Requirements
T
A
=
25°C
Symbol
t
W
(L), t
W
(H)
t
W
(L)
t
S
t
H
t
REM
T
A
=
–40°C
to +85°C
Guaranteed
Minimum
Units
ns
ns
ns
ns
ns
Parameter
Minimum Pulse Width (CK)
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time (CLR, PR)
V
CC
(V)
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
Typ.
5.0
5.0
5.0
0
3.5
5.0
5.0
5.0
0
3.5
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
www.fairchildsemi.com
5
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