Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
IN
= 12V (for MAX5975A, bring V
IN
up to 21V for startup), V
CS
= V
CSSC
= V
DITHER/SYNC
= V
FB
= V
FFB
= V
DCLMP
= V
GND
, V
EN
=
+2V, NDRV = SS = COMP = unconnected, R
RT
= 34.8kI, C
IN
= 1FF, T
A
= -40NC to +85NC, unless otherwise noted. Typical values
are at T
A
= +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MAX5975A
MAX5975B
MIN
19.1
9.4
6.65
TYP
19.8
9.8
7
MAX
20.4
10.25
7.35
UNITS
UNDERVOLTAGE LOCKOUT/STARTUP (IN)
Bootstrap UVLO Wakeup Level
Bootstrap UVLO Shutdown
Level
IN Supply Current in
Undervoltage Lockout
IN Supply Current After Startup
ENABLE (EN)
Enable Threshold
Input Current
OSCILLATOR (RT)
RT Bias Voltage
NDRV Switching Frequency
Range
NDRV Switching Frequency
Accuracy
Maximum Duty Cycle
D
MAX
f
SW
= 250kHz
V
RT
f
SW
100
-8
81
82.5
1.23
600
+8
84
V
kHz
%
%
V
ENR
V
ENF
I
EN
V
EN
rising
V
EN
falling
1.17
1.09
1.215
1.14
1.26
1.19
1
V
FA
V
INUVR
V
INUVF
V
IN
rising
V
IN
falling
V
IN
= +18V (for MAX5975A);
V
IN
= +9V (for MAX597BA),
when in bootstrap UVLO
V
IN
= +12V
V
V
I
START
I
C
100
1.8
150
3
FA
mA
2
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 12V (for MAX5975A, bring V
IN
up to 21V for startup), V
CS
= V
CSSC
= V
DITHER/SYNC
= V
FB
= V
FFB
= V
DCLMP
= V
GND
, V
EN
=
+2V, NDRV = SS = COMP = unconnected, R
RT
= 34.8kI, C
IN
= 1FF, T
A
= -40NC to +85NC, unless otherwise noted. Typical values
are at T
A
= +25NC.) (Note 2)
PARAMETER
SYNCHRONIZATION (SYNC)
Synchronization Logic-High
Input
Synchronization Pulse Width
Synchronization Frequency
Range
Maximum Duty Cycle During
Synchronization
DITHERING RAMP GENERATOR (DITHER)
Charging Current
Discharging Current
Ramp’s High Trip Point
Ramp’s Low Trip Point
SOFT-START AND RESTART (SS)
Charging Current
I
SS-CH
I
SS-D
Discharging Current
I
SS-DH
V
SS
= 2V, normal shutdown
(V
EN
< V
ENF
or V
IN
< V
INUVF
),
V
SS
= 2V, hiccup mode discharge for
t
RESTART
(Note 3)
9.5
0.65
1.6
10
1.34
2
10.5
2
2.4
FA
mA
FA
V
DITHER
= 0V
V
DITHER
= 2.2V
45
43
50
50
2
0.4
55
57
FA
FA
V
V
f
SYNCIN
1.1 x
f
SW
D
MAX
x f
SYNC
/
f
SW
V
IH-SYNC
2.91
50
2x
f
SW
V
ns
kHz
%
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5975A/MAX5975B
Discharge Threshold to Disable
Hiccup and Restart
Minimum Restart Time During
Hiccup Mode
Normal Operating High Voltage
Duty-Cycle Control Range
DUTY-CYCLE CLAMP (DCLMP)
DCLMP Input Current
Duty-Cycle Control Range
NDRV DRIVER
Pulldown Impedance
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
Rise Time
V
SS-DTH
t
RSTRT-MIN
V
SS-HI
V
SS-DMAX
I
DCLMP
V
DCLMP-R
D
MAX
(typ) = (V
SS-DMAX
/2.43V)
V
DCLMP
= 0 to 5V
V
DCLMP
= 0.5V
D
MAX
(typ) =
1 - (V
DCLMP/
2.43V)
V
DCLMP
= 1V
V
DCLMP
= 2V
0
-100
75
56
17
0.15
1024
5
2
0
77.3
58
18.6
1.9
4.7
1
0.65
+100
79.5
60
20.5
3.4
8.3
V
Clock
Cycles
V
V
nA
%
R
NDRV-N
R
NDRV-P
I
NDRV
(sinking) = 100mA
I
NDRV
(sourcing) = 50mA
I
I
A
A
ns
ns
t
NDRV-F
t
NDRV-R
C
NDRV
= 1nF
C
NDRV
= 1nF
14
27
3
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAX5975A/MAX5975B
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 12V (for MAX5975A, bring V
IN
up to 21V for startup), V
CS
= V
CSSC
= V
DITHER/SYNC
= V
FB
= V
FFB
= V
DCLMP
= V
GND
, V
EN
=
+2V, NDRV = SS = COMP = unconnected, R
RT
= 34.8kI, C
IN
= 1FF, T
A
= -40NC to +85NC, unless otherwise noted. Typical values
are at T
A
= +25NC.) (Note 2)
PARAMETER
Cycle-by-Cycle Peak
Current-Limit Threshold
Number of Consecutive Peak
Current-Limit Events to Hiccup
Current-Sense Leading-Edge
Blanking Time
Propagation Delay from
Comparator Input to NDRV
Minimum On-Time
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
PWM COMPARATOR
Comparator Offset Voltage
Current-Sense Gain
Current-Sense Leading-Edge
Blanking Time
Comparator Propagation Delay
ERROR AMPLIFIER
FB Reference Voltage
FB Input Bias Current
Voltage Gain
Transconductance
Transconductance Bandwidth
Source Current
Sink Current
FREQUENCY FOLDBACK (FFB)
V
CSAVG
-to-FFB Comparator
Gain
FFB Bias Current
NDRV Switching Frequency
During Foldback
I
FFB
f
SW-FB
V
FFB
= 0V, V
CS
= 0V (not in FFB mode)
26
10
30
f
SW
/2
33
V/V
FA
kHz
V
REF
I
FB
A
EAMP
g
M
BW
Open loop (typical gain = 1) -3dB
frequency
V
FB
= 1V, V
COMP
= 2.5V
V
FB
= 1.75V, V
COMP
= 1V
300
300
1.8
V
FB
when I
COMP
= 0, V
COMP
= 2.5V
V
FB
= 0 to 1.75V
1.202
-500
80
2.66
30
375
375
455
455
3.5
1.215
1.227
+100
V
nA
dB
mS
MHz
FA
FA
V
PWM-OS
A
CS-PWM
t
CSSC-BLANK
t
PWM
V
COMP
- V
CSSC
DV
COMP
/DV
CSSC
(Note 4)
From NDRV rising edge
Change in V
CSSC
= 10mV (including
internal leading-edge blanking)
1.35
3.1
1.7
3.33
115
150
2
3.6
V
V/V
ns
ns
Current ramp’s peak added to CSSC
input per switching cycle
47
52
58
FA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-LIMIT COMPARATORS (CS)
V
CS-PEAK
N
HICCUP
t
CS-BLANK
From NDRV rising edge
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
100
375
393
8
115
410
mV
Events
ns
t
PDCS
t
ON-MIN
35
150
200
ns
ns
Note 2:
The devices are 100% production tested at T
A
= +25NC. Limits over temperature are guaranteed by design.
Note 3:
See the
Output Short-Circuit Protection with Hiccup Mode
section.
Note 4:
The parameter is measured at the trip point of latch with V
模拟与混合信号
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