Ordering number : ENA0756A
STK672-610
Thick-Film Hybrid IC
2-phase Stepping Motor Driver
Overview
http://onsemi.com
The STK672-610 is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
•
Office photocopiers, printers, etc.
Features
•
The motor speed can be controlled by the frequency of an external clock signal.
•
2-phase excitation or 1-2 phase excitation is selected according to switching the state of the MODE1 pin (low or high).
•
The excitation mode is set at the rising edge of the clock signal when the MODE2 pin is High, or at the rising edge or
falling edge when the MODE2 pin is Low.
•
The phase is maintained even if the excitation mode is switched in the middle of operation.
•
The direction of rotation can be changed by applying a High or Low signal to the CWB pin used to select the direction
of rotation.
•
Supports schmitt input for 2.5V high level input.
•
Incorporating a current detection resistor (0.089Ω: resistor tolerance ±2%), motor current can be set using two
external resistors.
•
Equipped with an ENABLE pin that, during clock input, allows motor output to be cut-off and resumed later while
maintaining the same excitation timing.
Semiconductor Components Industries, LLC, 2013
June, 2013
62911HKPC 018-08-0105/71608HKIM No. A0756-1/19
STK672-610
Specifications
Absolute Maximum Ratings
at Tc = 25°C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Output current
Allowable power dissipation 1
Allowable power dissipation 2
Operating substrate temperature
Junction temperature
Storage temperature
Symbol
VCC max
VDD max
VIN max
IOH max
PdMF max
PdPK max
Tc max
Tj max
Tstg
No signal
No signal
Logic input pins
VDD=5V, CLOCK≥200Hz
With an arbitrarily large heat sink. Per MOSFET
No heat sink
Conditions
Ratings
52
-0.3 to +7.0
-0.3 to +7.0
4.0
10.2
3.1
105
150
-40 to +125
unit
V
V
V
A
W
W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges
at Ta = 25°C
Parameter
Operating supply voltage 1
Operating supply voltage 2
Input high voltage
Input low voltage
Output current 1
Output current 2
Symbol
VCC
VDD
VIH
VIL
IOH1
IOH2
With signals applied
With signals applied
Pins 10, 12, 13, 14, 15, 17
Pins 10, 12, 13, 14, 15, 17
Tc=105°C, CLOCK≥200Hz,
Continuous operation, duty=100%
Tc=80°C, CLOCK≥200Hz,
Continuous operation, duty=100%,
See the motor current (IOH) derating curve
CLOCK frequency
Phase driver withstand voltage
Recommended operating
substrate temperature
Recommended Vref range
Vref
Tc=105°C
fCL
VDSS
Tc
Minimum pulse width: at least 10μs
ID=1mA (Tc=25°C)
No condensation
0 to 50
100min
0 to 105
0.14 to 1.31
kHz
V
°C
V
3.3
A
Conditions
Ratings
10 to 42
5±5%
2.5 to VDD
0 to 0.6
3.0
unit
V
V
V
V
A
Refer to the graph for each conduction-period tolerance range for the output current and brake current.
Electrical Characteristics
at Tc = 25°C, VCC = 24V, VDD = 5.0V
Parameter
VDD supply current
Output average current
FET diode forward voltage
Output saturation voltage
Input leak current
Vref input bias current
PWM frequency
Symbol
ICCO
Ioave
Vdf
Vsat
IIL
IIB
fc
Conditions
Pin 9 current CLOCK=GND
R/L=1Ω/0.62mH in each phase
If=1A (RL=23Ω)
RL=23Ω
Pins 10, 12, 13, 14, 15, 17
=GND and 5V
Pin 19 =1.0V
35
204
45
0.629
min
typ
5.0
0.694
1.0
0.26
max
9
0.768
1.6
0.38
±10
216
56
unit
mA
A
V
V
μA
μA
kHz
*Ioave values are for when the lead frame of the product is soldered to the mounting substrate.
Notes: A fixed-voltage power supply must be used.
No. A0756-2/19
STK672-610
Precautions
[Damage to the internal MOSFET]
•
The RESETB pin must be fixed low when applying 5V power. If the RESETB pin is allowed to go high at the same
time as the 5V power, simultaneous ON of the output phase will result, causing damage to the internal MOSFET.
[GND wiring]
•
To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18
(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.
•
If the driver region VSS pin (Pin 16), S.G pin (Pin 18), P.G1 pin (Pin 2), and P.G2 pin (Pin 6) cannot be connected
to a single ground, make sure to connect the VSS pin to the control system S.GND, and the S.G pin to the P.G1 pin
and P.G2 pin.
[Input pins]
•
If VDD is not being applied to the hybrid IC, do not apply voltage to input Pins 10, 12, 13, 14, 15, or 17. In addition,
if VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to VSS, Pin 16,
and do not apply a voltage greater than or equal to VDD voltage.
•
Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal
block diagram.
•
Insert resistor RO3 (47 to 100Ω) so that the discharge energy from capacitor CO4 is not directly applied to the CMOS
IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6V (when If = 0.1A),
this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without
problem.
•
Both TTL and CMOS levels are used for the pin 10, 12, 13, 15 and 17 inputs.
•
Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 15, and 17 are
used as inputs, a 1 to 15kΩ pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.6V at Low level (less than 0.6V at Low level when IOL=5mA).
•
If input pins are connected to GND (VSS) using a pull-down resistor, be sure to mount a resistor having a resistance
of 120Ω or less. If designs call for a pull-down resistor having a resistance in the range 120Ω to 30kΩ, be absolutely
sure to mount a 1,000pF capacitor between the input pins and the VSS Pin. Because sufficient VIL cannot be
maintained due to the effect of input leak current, IIL=±10μA max, do not connect a pull-down resistor having a
resistance of 30kΩ or higher.
•
The sample application circuit includes a simple reset circuit using D1, R03, C02, and R04. If 5V power rises while
voltage still remains in C02, the reset signal cannot be detected as LOW and the driver may be damaged because ON
operations result at the same time that driver output is in A or AB phase or B or BB phase. The voltage of C02 must
therefore be less than 0.6V when the 5V power rises.
In addition, if a RESETB signal is to be input based on an external signal such as the CLOCK signal, RESETB must
always be fixed to a Low level when the 5V power signal rises.
•
To prevent malfunction due to chopping noise, we recommend that you mount a 1000pF capacitor between Pin 16 and
each of the input Pins 10, 12, 13, 14, 15, and 17. Be sure to mount the capacitor as close as possible to the pins of
hybrid IC.
If input is fixed Low, directly connect to Pin 16.
If input is fixed High, directly connect to the 5V power line.
[Current setting Vref]
•
Considering the specifications of the Vref input bias current, IIB, a value of 1kΩ or less is recommended for R02.
•
If the motor current is temporarily reduced, the circuit given below (STK672-600: IOH>0.2A, STK672-610:
IOH>0.3A) is recommended.
•
Although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection
function to ensure that the current does not exceed the maximum output current, IOH max. If Vref is mistakenly set to
a voltage that exceeds IOH max, the driver will be damaged by overcurrent.
No. A0756-5/19
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