AS4C64M16D3L-12BAN
Features
•
JEDEC Standard Compliant
•
Power supplies: V
DD
& V
DDQ
= +1.35V
•
Backward compatible to V
DD
& V
DDQ
= 1.5V ±0.075V
•
Automotive temperature: -40~105
°
C (TC)
•
AEC-Q100 Compliant
•
Supports JEDEC clock jitter specification
•
Fully synchronous operation
•
Fast clock rate: 800MHz
•
Differential Clock, CK & CK#
•
Bidirectional differential data strobe
- DQS & DQS#
•
8 internal banks for concurrent operation
•
8n-bit prefetch architecture
•
Pipelined internal architecture
•
Precharge & active power down
•
Programmable Mode & Extended Mode registers
•
Additive Latency (AL): 0, CL-1, CL-2
•
Programmable Burst lengths: 4, 8
•
Burst type: Sequential / Interleave
•
Output Driver Impedance Control
•
8192 refresh cycles / 64ms
- Average refresh period
7.8μs @ -40°C
≦TC≦
+85°C
3.9μs @ +85°C
＜TC≦
+105°C
Overview
The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 1Gb chip is organized as 8Mbit x 16 I/Os x 8
bank devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to 1600 Mb/
sec/pin for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling). All I/Os
are synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.35V
-0.067V /+0.1V power supply and are available in
BGA packages.
•
Write Leveling
•
ZQ Calibration
•
Dynamic ODT (Rtt_Nom & Rtt_WR)
•
RoHS compliant
•
Auto Refresh and Self Refresh
•
96-ball 8 x 13 x 1.0mm FBGA package
- Pb and Halogen Free
Table 1. Ordering Information
Part Number
AS4C64M16D3L-12BAN
Org
64Mx16
Temperature
Automotive-40°C to 105°C
MaxClock (MHz)
800
Package
96-ball FBGA
Table 2. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800MHz
CAS Latency
11
tRCD (ns)
tRP (ns)
13.75
13.75
Confidential
-2-
Rev.1.0 March 2016
AS4C64M16D3L-12BAN
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands
to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination,
and some other events are not captured in full detail
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
E
Self
Refresh
from any
RESET
state
ZQ
Calibration
ZQCL,ZQCS
Idle
SR
ZQCL
MRS
SR
X
REF
Refreshing
PD
ACT
E
PD
X
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Active
Power
Down
PD
X
Activating
Precharge
Power
Down
PD
E
Bank
Activating
RE
ITE
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
A
W
T
RI
AD
WR
WRITE
READ
E
Writing
READ
WRITE
Reading
RE
AD
A
WRITE A
READ A
IT
WR
EA
RE
A
DA
PRE, PREA
Writing
P
RE
,P
PR
E,
PR
EA
Reading
RE
A
Automatic Sequence
Command Sequence
Precharging
Confidential
-5-
Rev.1.0 March 2016
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