ST7538Q
FSK power line transceiver
General features
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Half duplex frequency shift keying (FSK)
transceiver
Integrated power line driver with programmable
voltage and current control
Programmable interface:
– Synchronous
– Asynchronous
Single supply voltage (from 7.5 up to 12.5V)
Very low power consumption (Iq = 5mA)
Integrated 5V voltage regulator (up to 50mA)
with short circuit protection
Integrated 3.3V voltage regulator (up to 50mA)
with short circuit protection
3.3V or 5V digital supply
8 programmable transmission frequencies
Programmable baud rate up to 4800BPS
Receiving sensitivity up to 250µVrms
Suitable to application in accordance with EN
50065 CENELEC specifications
Carrier or preamble detection
Band in use detection
Programmable 24 or 48 bit register with
security checksum
Mains zero crossing detection and
synchronization
Watchdog timer
Output voltage freeze
8 or 16 bit header recognition
UART/SPI host interface
ST7537 compatible
TQFP44 Slug Down
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Description
The ST7538Q is a Half Duplex
synchronous/asynchronous FSK Modem
designed for power line communication network
applications. It operates from a single supply
voltage and integrates a line driver and two linear
regulators for 5V and 3.3V. The device operation
is controlled by means of an internal register,
programmable through the synchronous serial
interface. Additional functions as watchdog, clock
output, output voltage and current control,
preamble detection, time-out, band in use are
included. Realized in Multipower BCD5
technology that allows to integrate DMOS, Bipolar
and CMOS structures in the same chip.
Order codes
Part number
ST7538Q
ST7538QTR
July 2006
Package
TQFP44 Slug Down
TQFP44 Slug Down
Rev 1
Packaging
Tube
Tape and reel
1/44
www.st.com
44
Contents
ST7538Q
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ST7538Q mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1
Communication between host and ST7538Q . . . . . . . . . . . . . . . . . . . . 20
Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.1
5.7.2
5.7.3
5.7.4
High sensitivity mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Synchronization recovery system (PLL) . . . . . . . . . . . . . . . . . . . . . . . . 23
Carrier/preamble detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Header recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8
5.9
5.10
5.11
Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8.1
Automatic Level Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Detection method and Rx Sensitivity in UART mode . . . . . . . . . . . . . . . . 35
2/44
ST7538Q
Contents
6
Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Zero crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Reg OK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5V and 3.3V voltage regulators and power good function . . . . . . . . . . . . 39
Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
Block diagram
ST7538Q
1
Figure 1.
Block diagram
Block diagram
AVdd AVss
TEST1
TEST2
BU
RxFo
CD/PD
CARRIER
DETECTION
TEST
BU
AGC
RxD
CLR/T
PLL
DIGITAL
FILTER
FSK
DEMOD
IF
FILTER
FILTER
AMPL
UART/SPI
REG/DATA
RxTx
TxD
FSK
MODULATOR
DAC
TX
FILTER
ALC
VOLTAGE
CONTROL
PLI
Vsense
ATO
ATOP1
ATOP2
+
-
VREG
PAVcc
Vdc
PG
RAI
SERIAL
INTERFACE
FILTER
CONTROL
REGISTER
CURRENT
CONTROL
CL
REGOK
OSC
TIME BASE
ZC
OP-AMP
XOut
XIn
WD
TOUT
RSTO
MCLK ZCout
ZCin C_OUT
CMINUS CPLUS
DVdd DVss
D03IN1407A
4/44
ST7538Q
Pin settings
2
2.1
Pin settings
Pin connection
Figure 2.
Pin Connection
(Top view)
REG_DATA
C_MINUS
C_OUT
C_PLUS
REG_OK
GND
TEST1
35
N.C.
PG
44
43
42
41
40
N.C.
39
38
37
36
CD_PD
DVSS
RXD
RxTx
TXD
GND
TOUT
CLR/T
BU
DVDD
MCLK
N.C.
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VDC
RAI
RXFO
TEST2
VSENSE
AVDD
XIN
XOUT
SGND
ATO
CL
RSTO
UART/SPI
WD
ZCOUT
ZCIN
N.C.
DVSS
ATOP1
PAVSS
ATOP2
PAVCC
D01IN1312
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