19-2006; Rev 0; 5/01
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
General Description
The MAX105 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of
in-phase (I) and quadrature (Q) baseband signals. The
MAX105 converts the analog signals of both I and Q
components to digital outputs at 800Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 200MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX105 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.4dB signal-to-noise
plus distortion (SINAD) with a 200MHz analog input sig-
nal and a sampling speed of 800MHz. A fully differen-
tial comparator design and encoding circuits reduce
out-of-sequence errors, and ensure excellent
metastable performance of only one error per 10
16
clock
cycles.
In addition, the MAX105 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX105 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a lower-speed, 400Msps version of the
MAX105, please refer to the MAX107 data sheet.
o
Two Matched 6-Bit, 800Msps ADCs
o
Excellent Dynamic Performance
36.4dB SINAD at f
IN
≈
200MHz and
f
CLK
≈
800MHz
o
Typical INL and DNL: ±0.25LSB
o
Channel-to-Channel Phase Matching: ±0.2°
o
Channel-to-Channel Gain Matching: ±0.04dB
o
6:12 Demultiplexer reduces the Data Rates to
400MHz
o
Low Error Rate: 10
16
Metastable States at
800Msps
o
LVDS Digital Outputs in Two’s Complement
Format
Features
MAX105
Ordering Information
PART
MAX105ECS
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
80-Pin TQFP-EP
Block Diagram
I
PRIMARY
PORT
I ADC
I
AUXILIARY
PORT
Applications
VSAT Receivers
WLANs
Test Instrumentation
Communications Systems
MAX107
REF
Q
PRIMARY
PORT
Q ADC
Q
AUXILIARY
PORT
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
MAX105
ABSOLUTE MAXIMUM RATINGS
AV
CC
, AV
CC
I, AV
CC
Q and AV
CC
R to AGND............-0.3V to +6V
OV
CC
I and OV
CC
Q to OGND ...................................-0.3V to +4V
AGND to OGND ................................................... -0.3V to +0.3V
P0I± to P5I± and A0I± to A5I±
DREADY+, DREADY- to OGNDI .............-0.3V to OV
CC
I+0.3V
P0Q± to P5Q±, A0Q± to A5Q±
DOR+ and DOR- to OGNDQ ................-0.3V to OV
CC
Q+0.3V
REF to AGNDR...........................................-0.3V to AV
CC
R+0.3V
Differential Voltage Between INI+ and INI- ....................-2V, +2V
Differential Voltage Between INQ+ and INQ-.................-2V, +2V
Differential Voltage Between CLK+ and CLK- ...............-2V, +2V
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (T
A
= +70°C)
80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W
Operating Temperature Range
MAX105ECS .....................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead temperature (soldering, 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 802.816MHz, C
L
= 1µF to AGND at REF, R
L
= 100Ω ±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity
(Note 1)
Offset Voltage
Offset Matching Between ADCs
Input Open-Circuit Voltage
Input Open-Circuit Voltage
Matching
Common Mode Input Voltage
Range (Note 3)
Full-Scale Analog Input
Voltage Range (Note 4)
Input Resistance
Input Capacitance
Input Resistance Temperature
Coefficient
Full-Power Analog Input BW
REFERENCE OUTPUT
Reference Output Resistance
Reference Output Voltage
R
REF
√REF
Referenced to AGNDR
I
SOURCE
= 500µA
2.45
5
2.50
2.55
Ω
V
V
CM
V
FSR
R
IN
C
IN
TCR
IN
FPBW
-0.5dB
RES
INL
DNL
V
OS
OM
V
AOC
(V
INI+
- V
IN-
) - (V
INQ+
- V
INQ-
)
Signal + Offset w.r.t. AGND
1.85
0.76
1.7
0.8
2
1.5
150
400
No missing codes guaranteed
(Note 2)
(Note 2)
6
-1
-1
-1
-0.5
2.4
±0.2
±0.25
±0.25
±0.1
2.5
1
1
1
0.5
2.6
±7.5
3.05
0.84
Bits
LSB
LSB
LSB
LSB
V
mV
V
V
p-p
kΩ
pF
ppm/°C
MHz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (INI+, INI-, INQ+, INQ-)
2
_______________________________________________________________________________________
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 802.816MHz, C
L
= 1µF to AGND at REF, R
L
= 100Ω ±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C)
PARAMETER
CLOCK INPUTS (CLK+, CLK-)
Clock Input Resistance
Clock Input Resistance
Temperature Coefficient
Minimum Clock Input
Amplitude
Differential Output Voltage
Change in Magnitude of
V
OD
Between “0” and “1” States
Steady-State Common Mode
Output Voltage
Change in Magnitude of V
OC
Between “0” and “1” States
Differential Output Resistance
Output Current
DYNAMIC SPECIFICATION
Effective Number of Bits
(Note 8)
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
ENOB
f
IN
= 400.134MHz at
-0.5dB FS
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
SNR
f
IN
= 400.134MHz at
-0.5dB FS
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
THD
f
IN
= 400.134MHz at
-0.5dB FS
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
Spurious-Free Dynamic Range
SFDR
f
IN
= 400.134MHz at
-0.5dB FS
Differential
Single-ended
Differential
Differential
Single-ended
Differential
Differential
Single-ended
Differential
Differential
Single-ended
Differential
41
35
5.4
5.8
5.75
5.65
37
36.7
36.5
-44.5
-44.5
-41
45
45
41.5
dB
-41
dBc
dB
Bits
Short output together
Short to OGNDI = OGNDQ
V
OD
∆V
OD
V
OC(SS)
∆V
OC
80
2.5
25
1.125
R
CLK
TCR
CLK
500
CLK+ and CLK- to AGND
5
150
kΩ
ppm/°C
mV
p-p
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX105
LVDS OUTPUTS (P0I± TO P5I±, P0Q± TO P5Q±, A0I± TO A5I±, A0Q± TO A5Q±, DREADY+, DREADY-, DOR+, DOR-)
247
400
±25
1.375
±25
160
mV
mV
V
mV
Ω
mA
Signal-to-Noise Ratio
(Notes 10, 11)
Total Harmonic Distortion
(Note 11)
_______________________________________________________________________________________
3
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
MAX105
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 802.816MHz, C
L
= 1µF to AGND at REF, R
L
= 100Ω ±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C)
PARAMETER
Signal-to-Noise Plus Distortion
Ratio
SYMBOL
CONDITIONS
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
SINAD
f
IN
= 400.134MHz at
-0.5dB FS
TTIMD
XTLK
GM
PM
Differential
Single-ended
Differential
MIN
34
TYP
36.4
36.1
35.2
-52
-70
-0.3
-2
±0.04
±0.2
+0.3
+2
dBc
dB
dB
deg
Clock
Cycles
V
V
320
510
mA
mA
W
dB
dB
dB
MAX
UNITS
Two-Tone Intermodulation
Crosstalk Between ADCs
Gain Match Between ADCs
Phase Match Between ADCs
Metastable Error Rate
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Output Supply Current
Analog Power Dissipation
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
Aperture Jitter
CLK-to-DREADY Propagation
Delay
DREADY-to-DATA
Propagation Delay
f
IN1
= 124.1660MHz, f
IN2
= 126.1260MHz
at -7dBFS
f
INI
= 200.0180MHz, f
INQ
= 210.0140MHz
at -0.5dB FS
(Note 12)
(Note 12)
Less than 1 in 10
16
AV
CC_
OV
CC_
I
CC
OI
CC
P
DISS
CMRR
PSRR
AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R
OV
CC
I = OV
CC
Q
I
CC
= AI
CC
R + AI
CC
I + AI
CC
Q + AI
CC
OI
CC
= OI
CC
I + OI
CC
Q
V
IN_+
= V
IN_-
=
±0.1V
(Note 6)
AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R =
+4.75V to +5.25V (Note 7)
40
40
5
±5%
3.3
±10%
250
400
2.6
60
57
f
MAX
t
PWL
t
PWH
t
AD
t
AJ
t
PD1
t
PD2
(Note 13)
(Notes 5, 13)
800
0.56
0.56
100
1.5
1.5
0
120
300
Msps
ns
ns
ps
ps
RMS
ns
ps
4
_______________________________________________________________________________________
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 802.816MHz, C
L
= 1µF to AGND at REF, R
L
= 100Ω ±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C)
PARAMETER
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
LVDS Differential Skew
DREADY Rise-Time
DREADY Fall-Time
Primary Port Pipeline Delay
Auxiliary Port Pipeline Delay
t
RDATA
t
FDATA
t
SKEW1
t
RDREADY
t
FDREADY
t
PDP
t
PDA
SYMBOL
(Notes 5, 13)
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
Any differential pair
Any two LVDS output signals except DREADY
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
200
200
5
6
CONDITIONS
MIN
47
200
200
<65
<100
500
500
TYP
MAX
53
500
500
UNITS
%
ps
ps
ps
ps
ps
ps
Clock
Cycles
Clock
Cycles
MAX105
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
NL and DNL is measured using a sine-histogram method.
Input offset is the voltage required to cause a transition between codes 0 and -1.
Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input
voltage level does not matter.
The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting
algorithm (e.g. FFT).
Guaranteed by design and characterization.
Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-
mode voltage expressed in dB.
Measured with analog power supplies tied to the same potential.
Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Harmonic distortion components two through five are included in the total harmonic distortion specification.
Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of f
IN
= 200.0180 MHz.
Measured with a differential probe, 1pF capacitance.
_______________________________________________________________________________________
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