CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
Ω
ON resistance
Rev. 4 — 18 June 2012
Product data sheet
1. General description
This 11-bit bus switch is designed for 1.7 V to 1.9 V V
DD
operation and SSTL_18 select
input levels.
Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The
selection of the DIMM port to be connected to the Host port is controlled by a decoder
driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all
DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1
select one of four DIMM ports to be connected to their respective host port. When
disconnected, any DIMM port is terminated to the externally supplied voltage V
bias
by
means of an on-chip pull-down resistor of typically 400
Ω.
The ON-state connects the
Host port to the DIMM port through a 12
Ω
nominal series resistance. The design is
intended to have only one DIMM port active at any time.
The CBTU4411 can also be configured to support a differential strobe signal on
channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS
configuration input strobe enable (STREN) is HIGH, channel 10 is pulled up to
3
⁄
4
of V
DD
internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is
disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current
savings, pulling channel 10 to V
DD
. When strobe enable (STREN) is LOW, channel 10
behaves the same as all other channels.
The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltage
should be provided to input pin VREF at nominally 0.5V
DD
. This topology provides
accurate control of switching times by reducing dependency on select signal slew rates.
S0 and S1 are provided with selectable input termination to 0.5V
DD
(active when LVCMOS
input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1
inputs are pulled LOW.
The part incorporates a very low crosstalk design. It has a very low skew between outputs
(< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal
performance in DDR2 data bus applications.
Each switch has been optimized for connection to 1- or 2-rank DIMMs.
The low internal RC time constant of the switch allows data transfer to be made with
minimal propagation delay.
The CBTU4411 is characterized for operation from 0
°C
to +85
°C.
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
Ω
ON resistance
2. Features and benefits
Enable (EN) and select signals (S0, S1) are SSTL_18 compatible
Optimized for use in Double Data Rate 2 (DDR2) SDRAM applications
Suitable to be used with 400 Mbit/s to 800 Mbit/s, 200 MHz to 400 MHz DDR2 data
bus
Switch ON-resistance is designed to eliminate the need for series resistor to DDR2
SDRAM
12
Ω
ON-resistance
Controlled enable/disable times support fast bus turnaround
Pseudo-differential select inputs support accurate and low-skew control of switching
times
Selectable built-in termination resistors on the Sn inputs
Internal 400
Ω
pull-down resistors on xDPn port
VBIAS input for optimal DIMM-port pull-down when disabled
Configurable to support differential strobe with pull-up to
3
⁄
4
of V
DD
on channel 10
when idle
Low differential skew
Matched rise/fall slew rate
Low crosstalk data-data/data-DQM
Simplified 1 : 4 switch position control by 2-bit encoded input
Single input pin puts all bus switches in OFF (high-impedance) position
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 1500 V HBM per JESD22-A114 and 750 V CDM per
JESD22-C101
3. Ordering information
Table 1.
Ordering information
T
amb
= 0
°
C to +85
°
C.
Type number
CBTU4411EE
Package
Name
LFBGA72
Description
plastic low profile fine-pitch ball grid array package;
72 balls; body 7
×
7
×
1.05 mm
Version
SOT856-1
CBTU4411
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 June 2012
2 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
Ω
ON resistance
4. Functional diagram
HP0
SWITCH
SWITCH
SWITCH
SWITCH
0DP0
1DP0
2DP0
3DP0
HP10
SWITCH
SWITCH
0DP10
1DP10
SWITCH
SWITCH
2DP10
3DP10
VREF
V
DD
R
T
×
2
(1)
S0
R
T
×
2
(1)
S1
R
T
×
2
(1)
R
T
×
2
(1)
SWITCH
CONTROL
EN
TERM
STREN
002aae850
(1) Selectable.
Fig 1.
Functional diagram (positive logic)
V
DD
from
switch
control
RPU
HPn
A
RON
SWITCH
xDPn
B
Rpd
400
Ω
HP10
SWITCH
xDP10
Rpd
from
switch
control
VBIAS
002aae848
from
switch
control
VBIAS
002aae849
Fig 2.
Simplified schematic,
channel 0 to channel 9
Fig 3.
Simplified schematic, channel 10
CBTU4411
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 June 2012
3 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
Ω
ON resistance
5. Pinning information
5.1 Pinning
ball A1
index area
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
CBTU4411EE
002aae837
Transparent top view
Fig 4.
Pin configuration
1
A
B
C
D
E
F
G
H
J
K
L
S1
TERM
VREF
VBIAS
2DP10
1DP10
0DP10
3DP9
1DP9
0DP9
3DP8
2
STREN
S0
EN
GND
3DP10
HP10
GND
2DP9
HP9
GND
2DP8
3
V
DD
V
DD
4
0DP0
GND
5
1DP0
HP0
6
2DP0
3DP0
7
1DP1
0DP1
8
2DP1
HP1
9
3DP1
GND
10
0DP2
HP2
0DP3
HP3
2DP3
GND
HP4
2DP4
1DP5
11
1DP2
2DP2
3DP2
1DP3
3DP3
0DP4
1DP4
3DP4
0DP5
2DP5
3DP5
002aae838
HP8
1DP8
0DP8
3DP7
HP7
2DP7
0DP7
1DP7
GND
3DP6
HP6
2DP6
0DP6
1DP6
HP5
V
DD
Blank cell indicates no ball at that location.
Fig 5.
Ball mapping (transparent top view)
CBTU4411
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 June 2012
4 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
Ω
ON resistance
5.2 Pin description
Table 2.
Symbol
HP0 to HP10
Pin description
Pin
Description
B5, B8, B10, D10, Host ports
G10, K10, K8, K5,
K3, J2, F2
C2
LVCMOS level enable input (active LOW). When connected
HIGH, all DIMM ports will be disconnected (show a
high-impedance path) from the Host ports.
Strobe enable. LVCMOS level strobe enable input
(active HIGH). When tied LOW, channel 10 (HP10 and its
DP ports) functions identically to all other channels. When
tied HIGH, channel 10 is designated as the Strobe channel
(see
Section 6.1 “Function selection”, Figure 2
and
Figure 3).
Select inputs; type SSTL_18. See
Section 6.1 “Function
selection”.
Reference voltage for the pseudo-differential SSTL_18
select inputs (S0, S1).
Voltage bias for the DIMM port pull-down resistor (R
pd
).
LVCMOS level input pin activates termination resistance on
Sn inputs when HIGH; high-impedance when LOW.
DIMM port 0
DIMM port 1
DIMM port 2
DIMM port 3
DIMM port 4
DIMM port 5
DIMM port 6
DIMM port 7
DIMM port 8
DIMM port 9
DIMM port 10
Ground
Positive supply voltage
EN
STREN
A2
S0
S1
VREF
VBIAS
TERM
0DP0, 1DP0,
2DP0, 3DP0
0DP1, 1DP1,
2DP1, 3DP1
0DP2, 1DP2,
2DP2, 3DP2
0DP3, 1DP3,
2DP3, 3DP3
0DP4, 1DP4,
2DP4, 3DP4
0DP5, 1DP5,
2DP5, 3DP5
0DP6, 1DP6,
2DP6, 3DP6
0DP7, 1DP7,
2DP7, 3DP7
0DP8, 1DP8,
2DP8, 3DP8
0DP9, 1DP9,
2DP9, 3DP9
B2
A1
C1
D1
B1
A4, A5,
A6, B6
B7, A7,
A8, A9
A10, A11,
B11, C11
C10, D11,
E10, E11
F11, G11,
H10, H11
J11, J10,
K11, L11
K9, L9,
L8, L7
K6, L6,
L5, L4
K4, L3,
L2, L1
K1, J1,
H2, H1
0DP10, 1DP10, G1, F1,
2DP10, 3DP10 E1, E2
GND
V
DD
B4, B9, D2, F10,
G2, K2, K7
A3, B3, L10
CBTU4411
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 June 2012
5 of 21
FPGA/CPLD
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