NXP Semiconductors
Data Sheet: Technical Data
KE1xFP100M168SF0
Rev. 2, 09/2016
Kinetis KE1xF with up to 512 KB
Flash
Up to 168 MHz ARM® Cortex®-M4 Based Microcontroller
The KE1xF microcontroller is built on the ARM
®
Cortex
®
-M4
processor with stronger performance and higher memory
densities in multiple packages. This device offers up to 168 MHz
performance with integrated single-precision floating point unit
(FPU) and digital signal processor (DSP). Embedded flash
memory sizes range from 256 KB to 512 KB.
MKE1xF512VLL16
MKE1xF512VLH16
MKE1xF256VLL16
MKE1xF256VLH16
100 LQFP (LL)
14x14x1.4 mm Pitch
0.5 mm
64 LQFP (LH)
10x10x1.4 mm Pitch
0.5 mm
Core Processor and System
Memory and memory interfaces
®
Cortex
®
-M4 core, supports up to 168 MHz
• ARM
• Up to 512 KB program flash with ECC
frequency with 1.25 Dhrystone MIPS per MHz
• Up to 64 KB SRAM with ECC
• ARM Core based on the ARMv7 Architecture and
• 64 KB FlexNVM with ECC for data flash and with
Thumb
®
-2 ISA
EEPROM emulation
• Integrated Digital Signal Processor (DSP)
• 4 KB FlexRAM for EEPROM emulation
• Configurable Nested Vectored Interrupt Controller
• 8 KB I/D cache to minimize performance impact of
(NVIC)
memory access latencies
• Single-precision Floating Point Unit (FPU)
• Boot ROM with built in bootloader
• 16-channel DMA controller extended up to 64 channels
Mixed-signal analog
with DMAMUX
• 3× 12-bit analog-to-digital converter (ADC) with up
Reliability, safety and security
to 16 channel analog inputs per module, up to 1M
• Error-correcting code (ECC) on Flash and SRAM
sps
memories
• 3× high-speed analog comparators (CMP) with
• System memory protection unit (MPU) module
internal 8-bit digital to analog converter (DAC)
• Flash Access Control (FAC)
• 1× 12-bit digital to analog converter (DAC)
• Cyclic Redundancy Check (CRC) generator module
Timing and control
• 128-bit unique identification (ID) number
• 4× Flex Timers (FTM) for PWM generation, offering
• Internal watchdog (WDOG) with independent clock
up to 32 standard channels
source
• 1× Low-Power Timer (LPTMR) working at Stop
• External watchdog monitor (EWM) module
mode, with flexible wake up control
• ADC self calibration feature
• 3× Programmable Delay Block (PDB) with flexible
• On-chip clock loss monitoring
trigger system, to provide accurate delay and trigger
Human-machine interface (HMI)
generation for inter-module synchronization
• Supports up to 92 interrupt request (IRQ) sources
• 1× Low-power Periodic Interrupt Timer (LPIT) with 4
• Up to 89 GPIO pins with interrupt functionality
independent channels, for general purpose
• 8 high drive pins
• Pulse Width Timer (PWT)
• Digital filters
• Real timer clock (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Clock interfaces
• 3 - 40 MHz fast external oscillator (OSC)
• 32 kHz slow external oscillator (OSC32)
• 48 - 60 MHz high-accuracy (up to 1%) fast internal
reference clock (FIRC) for high-speed run
• 8 MHz / 2 MHz high-accuracy (up to 3%) slow internal
reference clock (SIRC) for low-speed run
• 128 kHz low power oscillator (LPO)
• Phased lock loop (PLL)
• Up to 60 MHz DC external square wave input clock
• System clock generator (SCG)
• Real time counter (RTC)
Connectivity and communications interfaces
• TriggerMUX: for module inter-connectivity
• 3× low-power universal asynchronous receiver/
transmitter (LPUART) modules with DMA support
and working at Stop mode
• 2 low-power serial peripheral interface (LPSPI)
modules with DMA support and working at Stop
mode
• 2× low-power inter-integrated circuit (LPI2C)
modules with DMA support and working at Stop
mode
• Up to 2 ×FlexCAN modules, with flexible message
buffers and mailboxes
Power management
• FlexIO module for flexible and high performance
• Low-power ARM Cortex-M4 core with excellent energy
serial interfaces emulation
efficiency
Debug functionality
• Power management controller (PMC) with multiple
power modes: HSRun, Run, Wait, Stop, VLPR, VLPW
• Serial Wire JTAG Debug Port (SWJ-DP) combines
and VLPS
• Debug Watchpoint and Trace (DWT)
• Supports clock gating for unused modules, and specific
• Instrumentation Trace Macrocell (ITM)
peripherals remain working in low power modes
• Test Port Interface Unit (TPIU)
• POR, LVD/LVR
• Flash Patch and Breakpoints (FPB)
Operating Characteristics
• Voltage range: 2.7 to 5.5 V
• Ambient temperature range: –40 to 105 °C
Related Resources
Type
Selector
Guide
Product Brief
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
Resource
Solution Advisor
KE1xF512PB
1
KE1xFP100M168SF0RM
1
This document:
KE1xFP100M168SF0
The chip mask set Errata provides additional or corrective information for Kinetis_E_0N79P
1
a particular device mask set.
Package dimensions are provided in package drawings.
100-LQFP:
98ASS23308W
64-LQFP:
98ASS23234W
1. To find the associated resource, go to
http://www.nxp.com
and perform a search using this term.
2
NXP Semiconductors
Kinetis KE1xF with up to 512 KB Flash, Rev. 2, 09/2016
Kinetis KE1xF Sub-Family
ARM
®
Cortex
®
-M4
Core
System
MPU
Memories and Memory Interfaces
Program
flash
FlexMemory
RAM
Clocks
OSC
FIRC
eDMA
Debug
interfaces
Interrupt
controller
DSP
DMAMUX
TRGMUX
WDOG
EWM
Boot ROM
SIRC
PLL
OSC32
FPU
LPO
Security
and Integrity
CRC
Analog
12-bit ADC
x3
Timers
FlexTimer
8ch x4
PDB x3
Communication Interfaces
LPI
C
x2
LPUART
x3
LPSPI
x2
FlexCAN
upto x2
2
Human-Machine
Interface (HMI)
GPIO
upto 89
High drive
I/O (8 pins)
Digital filters
(all ports)
ECC
CMP x3
FAC
12-bit DAC
x1
LPIT, 4ch
LPTMR
PMC
SRTC
PWT
FlexIO
Figure 1. Functional block diagram
Kinetis KE1xF with up to 512 KB Flash, Rev. 2, 09/2016
3
NXP Semiconductors
Table of Contents
1 Ordering information............................................................... 5
2 Overview................................................................................. 5
2.1 System features...............................................................6
2.1.1
2.1.2
2.1.3
ARM Cortex-M4 core........................................ 6
NVIC..................................................................7
AWIC.................................................................7
5.1.1
5.1.2
5.1.3
5.1.4
Definitions......................................................... 42
Examples.......................................................... 42
Typical-value conditions....................................43
2.1.4
Memory............................................................. 8
2.1.5
Reset and boot..................................................8
2.1.6
Clock options.....................................................10
2.1.7
Security............................................................. 11
2.1.8
Power management.......................................... 12
2.1.9
Debug controller................................................13
2.2 Peripheral features.......................................................... 13
2.2.1
eDMA and DMAMUX........................................ 14
2.2.2
FTM...................................................................14
2.2.3
ADC...................................................................14
2.2.4
DAC...................................................................15
2.2.5
CMP.................................................................. 16
2.2.6
RTC...................................................................16
2.2.7
LPIT...................................................................17
2.2.8
PDB...................................................................17
2.2.9
LPTMR.............................................................. 17
2.2.10 CRC.................................................................. 18
2.2.11
2.2.12
2.2.13
2.2.14
LPUART............................................................ 18
LPSPI................................................................ 19
FlexCAN............................................................19
LPI2C................................................................ 20
Relationship between ratings and operating
requirements..................................................... 43
5.1.5
Guidelines for ratings and operating
requirements..................................................... 44
5.2 Ratings............................................................................ 44
5.2.1
Thermal handling ratings...................................44
5.2.2
Moisture handling ratings.................................. 45
5.2.3
ESD handling ratings........................................ 45
5.2.4
Voltage and current operating ratings............... 45
5.3 General............................................................................ 45
5.3.1
Nonswitching electrical specifications............... 46
5.3.2
Switching specifications.................................... 57
5.3.3
Thermal specifications...................................... 60
5.4 Peripheral operating requirements and behaviors...........63
5.4.1
System modules................................................63
5.4.2
Clock interface modules....................................64
5.4.3
Memories and memory interfaces.....................71
5.4.4
Security and integrity modules.......................... 74
5.4.5
Analog............................................................... 74
5.4.6
Communication interfaces.................................82
5.4.7
Debug modules................................................. 86
6 Design considerations.............................................................90
6.1 Hardware design considerations..................................... 90
6.1.1
Printed circuit board recommendations.............90
6.1.2
6.1.3
6.1.4
Power delivery system...................................... 91
Analog design................................................... 91
Digital design.....................................................92
2.2.15 FlexIO................................................................21
2.2.16 Port control and GPIO.......................................22
3 Memory map........................................................................... 24
4 Pinouts.................................................................................... 26
4.1 KE1xF Signal Multiplexing and Pin Assignments............ 26
4.2 Port control and interrupt summary................................. 29
4.3 Module Signal Description Tables................................... 30
4.4 Pinout diagram................................................................ 35
4.5 Package dimensions....................................................... 37
5 Electrical characteristics..........................................................42
5.1 Terminology and guidelines.............................................42
6.1.5
Crystal oscillator................................................95
6.2 Software considerations.................................................. 96
7 Part identification.....................................................................97
7.1 Description.......................................................................97
7.2 Format............................................................................. 97
7.3 Fields............................................................................... 97
7.4 Example...........................................................................97
8 Revision history.......................................................................98
4
NXP Semiconductors
Kinetis KE1xF with up to 512 KB Flash, Rev. 2, 09/2016
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
Comm
unicat
ion
FlexC
AN
2
2
2
2
1
1
1
1
0
0
0
0
Part number
Marking
(Line1/Line2)
Flash
(KB)
512
512
256
256
512
512
256
256
512
512
256
256
SRAM
(KB)
64
64
32
32
64
64
32
32
64
64
32
32
FlexNVM/
FlexRAM
(KB)
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
Pin
count
100
64
100
64
100
64
100
64
100
64
100
64
Packa
ge
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
GPIOs GPIOs ADC
(INT/H chann
D)
1
els
89
58
89
58
89
58
89
58
89
58
89
58
89/8
58/8
89/8
58/8
89/8
58/8
89/8
58/8
89/8
58/8
89/8
58/8
16
16
16
16
16
16
16
16
16
16
16
16
MKE18F512VLL
16
MKE18F512VL
H16
MKE18F256VLL
16
MKE18F256VL
H16
MKE16F512VLL
16
MKE16F512VL
H16
MKE16F256VLL
16
MKE16F256VL
H16
MKE14F512VLL
16
MKE14F512VL
H16
MKE14F256VLL
16
MKE14F256VL
H16
MKE18F512 /
VLL16
MKE18F512 /
VLH16
MKE18F256 /
VLL16
MKE18F256 /
VLH16
MKE16F512 /
VLL16
MKE16F512 /
VLH16
MKE16F256 /
VLL16
MKE16F256 /
VLH16
MKE14F512 /
VLL16
MKE14F512 /
VLH16
MKE14F256 /
VLL16
MKE14F256 /
VLH16
1. INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device.
Kinetis KE1xF with up to 512 KB Flash, Rev. 2, 09/2016
5
NXP Semiconductors
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