or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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pwr604_02.1
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Power Supply Sequence Controller and Monitor
The ispPAC-POWR604 device is specifically designed as a fully-programmable power supply sequencing controller
and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup-
plies. The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi-
tal logic functions and control state machines. The internal PLD connects to two programmable timers, special
purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either
an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as six independent comparators each with 192 programmable trip point set-
tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.
All six voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage lev-
els can be accounted for using various scale factors.
For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor.
Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly
affects trip-point accuracy. Therefore, the hysteresis is +/-16mV for 5V supplies and scales down to +/-3mV for 1.2V
supplies, or about 0.3% of the trip point.
The programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. The
architecture supports the sharing of product terms to enhance the overall usability.
The four output pins are open-drain outputs. These outputs can be used to drive enable lines for DC/DC converters
or other control logic associated with power supply control. The four outputs are driven from the macrocells.
Figure 1. ispPAC-POWR604 Block Diagram
ispPAC-POWR604
6
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
Analog
Inputs
6
Sequence
Controller
CPLD
20 I/P & 8
Macrocell
GLB
Comparator
Outputs
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
IN1
IN2
IN3
IN4
RESET
5
Digital
Inputs
250kHz
Internal
OSC
2 Timers
4
Logic
Outputs
OUT5
OUT6
OUT7
OUT8
CLKIO
2
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Name
NC
NC
NC
NC
VDD
IN1
IN2
IN3
IN4
RESET
VDDINP
OUT5
8
OUT6
8
OUT7
8
OUT8
NC
NC
COMP6
COMP5
COMP4
COMP3
COMP2
COMP1
TCK
POR
CLK
GND
TDO
TRST
TDI
TMS
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
NC
CREF
NC
NC
8
Pin Type
—
—
—
—
Power
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS input
Power
O/D Output
O/D Output
O/D Output
O/D Output
—
—
O/D Output
O/D Output
O/D Output
O/D Output
O/D Output
O/D Output
TTL/LVCMOS Input
O/D Output
Bi-directional I/O
Ground
TTL/LVCMOS Output
TTL/LVCMOS Input
TTL/LVCMOS Input
TTL/LVCMOS Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
—
Reference
—
—
—
—
—
—
Voltage Range
No Connect
No Connect
No Connect
No Connect
Description
2.25V-5.5V
VDDINP
1, 3
VDDINP
VDDINP
VDDINP
VDD
6
2.25V-5.5V
3
2.25V-5.5V
2
2.25V-5.5V
2
2.25V-5.5V
2
2.25V-5.5V
—
—
2.25V-5.5V
2
2.25V-5.5V
2
2.25V-5.5V
2
2.25V-5.5V
2
2.25V-5.5V
2.25V-5.5V
VDD
2.25V-5.5V
VDD
2, 5
VDD
VDD
VDD
VDD
0V-5.72V
4
0V-5.72V
4
0V-5.72V
4
0V-5.72V
4
0V-5.72V
0V-5.72V
—
1.17V
7
—
—
4
4
2
2
2
1, 3
1, 3
1, 3
Main Power Supply
Input 1
Input 2
Input 3
Input 4
PLD Reset Input, Active Low
Digital Inputs Power Supply
Open-Drain Output
Open-Drain Output
Open-Drain Output
Open-Drain Output
No Connect
No Connect
VMON6 Comparator Output (Open-Drain)
VMON5 Comparator Output (Open-Drain)
VMON4 Comparator Output (Open-Drain)
VMON3 Comparator Output (Open-Drain)
VMON2 Comparator Output (Open-Drain)
VMON1 Comparator Output (Open-Drain)
Test Clock (JTAG Pin)
Power-On-Reset Output
Clock Output (Open-Drain) or Clock Input
Ground
Test Data Out (JTAG Pin)
Test Reset, Active Low, 50k Ohm Internal Pull-up
(JTAG Pin, Optional Use)
Test Data In, 50k Ohm Pull-up (JTAG Pin)
Test Mode Select, 50k Ohm Internal Pull-up (JTAG
Pin)
Voltage Monitor Input 1
Voltage Monitor Input 2
Voltage Monitor Input 3
Voltage Monitor Input 4
Voltage Monitor Input 5
Voltage Monitor Input 6
No Connect
Reference for Internal Use, Decoupling Capacitor
(.1uf Required, CREF to GND)
No Connect
No Connect
3
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Pin Descriptions (Continued)
Number
42
43
44
Name
NC
NC
NC
—
—
—
Pin Type
—
—
—
Voltage Range
No Connect
No Connect
No Connect
Description
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.
2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
26 can only be pulled as high as VDD.
3. VDDINP can be chosen independent of V
DD.
It applies only to the four logic inputs IN1-IN4.
4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground).
5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design
time. In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be
≤
V
DD
). Multiple ispPAC-
POWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.
6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD
flip-flops
to zero, and may
turn “ON” or “OFF” the output pins, depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the
other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the
PLD logic to the initial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be
connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET
pin.
7. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional
external circuitry should be connected to this pin.
8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.
Symbol
VDD
VDD
INP
1
V
IN
2
VMON
V
TRI
T
S
T
A
T
SOL
Parameter
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V
MON
voltage monitor inputs
Tristated or open drain output, external voltage applied
(CLK pin 26 pull-up
≤
VDD).
Storage temperature
Ambient temperature with power applied
Maximum soldering temperature (10 sec. at 1/16 in.)
Conditions
—
—
—
—
—
—
—
—
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-65
-55
—
Max.
6.0
6.0
6.0
7.0
6.0
150
125
260
Units
V
V
V
V
V
°C
°C
°C
1. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V
DDINP
voltage.
4
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Recommended Operating Conditions
Symbol
V
DD
V
DDPROG
V
DDINP
2
V
IN
3
V
MON
Erase/Program
Cycles
T
APROG
T
A
Ambient temperature during
programming
Ambient temperature
Power applied - Industrial
Power applied - Automotive
2
Parameter
Core supply voltage at pin
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage digital inputs
Voltage monitor inputs V
MON1
- V
MON6
Conditions
During E cell programming
2
Min.
2.25
3.0
2.25
0
0
Max.
5.5
5.5
5.5
5.5
6.0
—
+85
+85
+125
Units
V
V
V
V
V
Cycles
°C
°C
°C
1
EEPROM, programmed at
V
DD
= 3.0V to 5.5V
-40°C to +85°C
1000
-40
-40
-40
1. The ispPAC-POWR604 device must be powered from 3.0V to 5.5V during programming of the E CMOS memory.
2. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltge for the given input logic range.
3. Digital inputs are tolerant up to 5.5V, independent of the V
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