Si53312
1 : 1 0 L
OW
J
I T T E R
U
NIVERSAL
B
U FF E R
/L
EVEL
T
RANSLATOR WITH
2 : 1 I
NPUT
M
UX
(<1.25 GH
Z
)
Features
10 differential or 20 LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range:
dc to 1.25 GHz
Any-format input with pin selectable
output formats: LVPECL, Low Power
LVPECL, LVDS, CML, HCSL,
LVCMOS
2:1 mux with hot-swappable inputs
Asynchronous output enable
Output clock division: /1, /2, /4
(/2 and /4 for dc to 725 MHz)
Low output-output skew: <70 ps
Low propagation delay variation:
<400 ps
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
Excellent power supply noise
rejection (PSRR)
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 28.
Applications
Pin Assignments
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
DIVA
1
2
3
4
5
6
7
8
9
10
11
Si53312
VDDOA
VDDOB
34
Q3
Q3
Q4
Q4
GND
Q5
Q5
43
42
41
40
39
38
37
Q6
Q6
36
35
44
33
32
31
30
DIVB
SFOUTB[1]
SFOUTB[0]
Q7
Q7
NC
Q8
Q8
Q9
Q9
CLK_SEL
Description
The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53312 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53312 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53312 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
SFOUTA[1]
SFOUTA[0]
Q2
Q2
GND
Q1
Q1
Q0
GND
PAD
29
28
27
26
25
24
23
Q0
NC
12
15
16
13
17
19
20
14
18
21
VDD
CLK0
CLK0
OEA
V
REF
OEB
CLK1
Patents pending
Functional Block Diagram
Power
Supply
Filtering
V
REF
Vref
Generator
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
DivA
CLK0
/CLK0
Q0, Q1, Q2, Q3, Q4
DIVB
CLK1
/CLK1
DivB
CLK_SEL
Switching
Logic
Q5, Q6, Q7, Q8, Q9
VDDOB
SFOUTB[1:0]
OEB
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 9/15
Copyright © 2015 by Silicon Laboratories
CLK1
NC
GND
NC
22
Si53312
Si53312
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Power Supply (V
DD
and V
DDOX
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Si53312 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
Rev. 1.0
Si53312
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML
Test Condition
Min
–40
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
Output Buffer Supply
Voltage*
V
DDOX
LVDS, CML, LVCMOS
2.38
2.97
2.97
1.71
2.38
2.97
LVPECL, low power LVPECL
2.38
2.97
HCSL
2.97
Typ
—
1.8
2.5
3.3
2.5
3.3
3.3
1.8
2.5
3.3
2.5
3.3
3.3
Max
85
1.89
2.63
3.63
2.63
3.63
3.63
1.89
2.63
3.63
2.63
3.63
3.63
Unit
°C
V
V
V
V
V
V
V
V
V
V
V
V
*Note:
Core supply V
DD
and output buffer supplies V
DDO
are independent. LVCMOS clock input is not supported for
V
DD
=
1.8V but is supported for LVCMOS clock output for
V
DDOX
= 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V”
Table 2. Input Clock Specifications
(V
DD
=1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High
Voltage
LVCMOS Input Low
Voltage
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK0 and CLK1 pins with
respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x
0.3
—
Unit
V
V
V
V
pF
Rev. 1.0
3
Si53312
Table 3. DC Common Characteristics
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz
Symbol
I
DD
I
DDOX
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
CMOS (1.8 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (2.5 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, C
L
= 5 pF, 200 MHz
Voltage Reference
Input High Voltage
Input Mid Voltage
Input Low Voltage
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
REF
V
IH
V
IM
V
IL
R
DOWN
R
UP
V
REF
pin
SFOUTx, DIVx, CLK_SEL, OEx
SFOUTx, DIVx
3-level input pins
SFOUTx, DIVx, CLK_SEL, OEx
CLK_SEL, DIVx, SFOUTx,
OEx, DIVx, SFOUTx
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
0.8 x
VDD
0.45 x
VDD
—
—
—
Typ
65
35
35
20
30
35
5
8
15
VDD/2
—
0.5 x
VDD
—
25
25
Max
100
—
—
—
—
—
—
—
—
—
—
0.55 x
VDD
0.2 x
VDD
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
kΩ
kΩ
Table 4. Output Characteristics (LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common Mode
Voltage
Single-Ended
Output Swing
Symbol
V
COM
V
SE
Test Condition
Min
V
DDOX
– 1.595
0.40
Typ
—
0.80
Max
V
DDOX
– 1.245
1.050
Unit
V
V
*Note:
Unused outputs can be left floating. Do not short unused outputs to ground.
4
Rev. 1.0
Si53312
Table 5. Output Characteristics (Low Power LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common
Mode Voltage
Single-Ended
Output Swing
Symbol
V
COM
V
SE
Test Condition
R
L
= 100
across
Qn and Qn
R
L
= 100
across
Qn and Qn
Min
V
DDOX
– 1.895
0.20
Typ
Max
V
DDOX
– 1.275
Unit
V
V
0.60
0.85
Table 6. Output Characteristics—CML
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
V
SE
Test Condition
Terminated as shown in Figure 8
(CML termination).
Min
200
Typ
400
Max
550
Unit
mV
Table 7. Output Characteristics—LVDS
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(V
DDO
= 2.5 V or
3.3V)
Output Common
Mode Voltage
(V
DDO
= 1.8 V)
Symbol
V
SE
V
COM1
Test Condition
R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 2.38 to 2.63 V, 2.97 to
3.63 V, R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 1.71 to 1.89 V,
R
L
= 100
Ω
across Q
N
and Q
N
Min
200
1.10
Typ
—
1.25
Max
490
1.35
Unit
mV
V
V
COM2
0.85
0.97
1.25
V
Table 8. Output Characteristics—LVCMOS
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Output Voltage High
Output Voltage Low
Symbol
V
OH
V
OL
Test Condition
Min
0.75 x V
DDOX
—
Typ
—
—
Max
—
0.25 x V
DDOX
Unit
V
V
*Note:
I
OH
and I
OL
per the Output Signal Format Table for specific
V
DDOX
and SFOUTx settings.
Rev. 1.0
5
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