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74LV86
Quad 2-input exclusive-OR gate
Rev. 03 — 27 November 2007
Product data sheet
1. General description
The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC86 and 74HCT86.
The 74LV86 provides a quad 2-input exclusive-OR function.
2. Features
s
s
s
s
s
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV86N
74LV86D
74LV86DB
74LV86PW
74LV86BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
4. Functional diagram
1
2
=1
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
4
1Y
3
5
=1
6
2Y
6
9
=1
8
3Y
8
10
4Y
11
12
13
=1
11
mna787
mna786
Fig 1. Logic symbol
Fig 2. IEC logic symbol
A
Y
B
mna788
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74LV86
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aad103
14 V
CC
13 4B
12 4A
terminal 1
index area
1B
1Y
2A
2B
2
3
4
5
6
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
3Y
8
86
11 4Y
10 3B
9
8
3A
3Y
V
CC(1)
7
GND
2Y
1
1A
001aah098
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
74LV86_3
Fig 5. Pin configuration DHVQFN14
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 27 November 2007
2 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
L
H
H
nB
L
H
L
H
Output
nY
L
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Conditions
Min
−0.5
-
-
-
-
−50
−65
Max
+7.0
±20
±50
±25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
°C
74LV86_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 27 November 2007
3 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
P
tot
Parameter
total power dissipation
DIP14 package
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
[5]
Conditions
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
[5]
Min
-
-
-
-
Max
750
500
500
500
Unit
mW
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
°C.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
74LV86_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 27 November 2007
4 of 15
嵌入式系统
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