3.3 VOLT CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING
64 x 36 x 2
FEATURES:
♦
♦
♦
♦
♦
♦
♦
♦
IDT72V3614
Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
♦
Supports clock frequencies up to 83 MHz
♦
Fast access times of 8 ns
♦
Free-running CLKA and CLKB can be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single
clock edge is permitted)
♦
Mailbox bypass Register for each FIFO
♦
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
♦
Selection of Big- or Little-Endian format for word and byte bus
sizes
Three modes of byte-order swapping on port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
EFA
,
FFA
,
AEA
, and
AFA
flags synchronized by CLKA
EFB
,
FFB
,
AEB
, and
AFB
flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
♦
Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
♦
Pin and functionally compatible version of the 5V operating
IDT723614
♦
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Mail 1
Register
Parity
Gen/Check
MBF1
PEFB
PGB
Bus-Matching &
Byte Swapping
Parity
Generation
Input
Register
RAM
ARRAY
Output
Register
36
RST
ODD/
EVEN
Device
Control
64 x 36
Write
Pointer
FFA
AFA
36
Read
Pointer
EFB
AEB
B
0
-B
35
Status Flag
Logic
FIFO1
Programmable Flag
Offset Register
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
FS0
FS1
A
0
- A
35
EFA
AEA
FFB
AFB
36
Bus-Matching &
Byte Swapping
Parity
Generation
Output
Register
RAM
ARRAY
64 x 36
PGA
Parity
Gen/Check
Mail 2
Register
PEFA
MBF2
Input
Register
Port-B
Control
Logic
4663 drw 01
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
JULY 2000
1
©
2000
Integrated Device Technology, Inc.
DSC-4663/-
IDT72V3614 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
Commercial Temperature Range
indicate when a selected number of words is stored in memory. FIFO data on
port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice
of Big- or Little-Endian configurations. Three modes of byte-order swapping are
possible with any bus size selection. Communication between each port can
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored. Parity is checked passively on
each port and may be ignored if not desired. Parity generation can be selected
for data read from each port. Two or more devices can be used in parallel to
create wider data paths.
DESCRIPTION:
The IDT72V3614 is a pin and functionally compatible version of the
IDT723614, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is monolithic, high-speed, low-power CMOS
bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz
and has read access times as fast as 8 ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (Almost-Full and Almost-Empty) to
V
CC
A
24
A
25
A
26
GND
A
27
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
V
CC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
GND
AEA
EFA
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
GND
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
SIZ0
MBF1
GND
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
AFB
PIN CONFIGURATIONS
*
GND
AEB
EFB
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
*
4663 drw 02
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP
(2)
NOTES:
1. NC - No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
(PQ132-1, order code: PQF)
TOP VIEW
2
IDT72V3614 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
Commercial Temperature Range
The Full Flag (FFA,
FFB)
and Almost-Full flag (AFA,
AFB)
of a FIFO are
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (EFA,
EFB)
and Almost-Empty (AEA,
AEB)
flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT72V3614 is characterized for operation from 0°C to 70°C. Industrial
temperature range (–40°C to +85°C) is available by special order. This device
is fabricated using IDT's high speed, submicron CMOS technology.
DESCRIPTION (Continued):
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors and/or buses con-
trolled by a synchronous interface.
PIN CONFIGURATIONS (Continued)
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
32
A
33
A
34
A
35
GND
B
35
B
34
B
33
B
32
B
31
B
30
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
B
23
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
EFA
AEA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EFB
AEB
AFB
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF
2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
SIZ0
MBF
1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
TQFP (PN120-1, order code: PF)
TOP VIEW
3
4663 drw 03
IDT72V3614 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
Commercial Temperature Range
PIN DESCRIPTION
Symbol
A0-A35
AEA
AEB
AFA
AFB
B0-B35
BE
CLKA
CLKB
Name
Port A Data
Port A Almost-
Empty Flag
Port B Almost-
Empty Flag
I/O
I/O
36-bit bidirectional data port for side A.
Description
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit words in
(Port A) FIFO2 is less than or equal to the value in the offset register, X.
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit words in
(Port B) FIFO1 is less than or equal to the value in the offset register, X.
Port A Almost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty
Flag
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
Port B Almost-Full
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of 36-bit empty
Flag
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
Port B Data
Big-Endian Select
Port A Clock
Port B Clock
I/O
I
I
I
36-bit bidirectional data port for side B.
Selects the bytes on port B used during byte or word data transfer. A LOW on
BE
selects the most significant
bytes on B0-B35 for use, and a HIGH selects the least significant bytes.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB.
EFA, FFA, AFA,
and
AEA
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB.
EFB, FFB, AFB,
and
AEB
are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
CSA
CSB
EFA
Port A Chip Select
Port B Chip Select
Port A Empty Flag
I
I
O
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
isLOW, FIFO2 is empty, and
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when
EFA
is
HIGH.
EFA
is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
O
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
is LOW, the FIFO1 is empty, and
(Port B) and reads from its memory are disabled. Data can be read from FIFO1 to the output register when
EFB
is
HIGH.
EFB
is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO1 memory.
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
EFB
Port B Empty Flag
ENA
ENB
FFA
Port A Enable
Port B Enable
Port A Full Flag
O
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is LOW, FIFO1 is full, and writes
(Port A) to its memory are disabled.
FFA
is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after reset.
O
FFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
FFB
is LOW, FIFO2 is full, and writes
(Port B) writes to its memory are disabled.
FFB
is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after reset.
I
I
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1, which selects one of four preset
values for the Almost-Full flag and Almost-Empty flag offset.
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level
selects FIFO2 output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while
MBF1
is set LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH.
MBF1
is set HIGH when the
device is reset.
FFB
Port B Full Flag
FS1, FS0 Flag-Offset
Selects
MBA
Port A Mailbox
Select
Mail1 Register
Flag
MBF1
O
4
IDT72V3614 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
Commercial Temperature Range
PIN DESCRIPTION (Continued)
Symbol
MBF2
Name
Mail2 Register
Flag
Odd/Even
Parity Select
Port A Parity
Error Flag
I/O
O
Description
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while
MBF2
is set LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA
when a port A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
ODD/
EVEN
PEFA
I
O
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW. Bytes are organized as A0-A8,
(Port A) A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type
of parity checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA
LOW, MBA HIGH, and PGA HIGH, the
PEFA
flag is forced HIGH regardless of the A0-A35 inputs.
PEFB
Port B Parity
Error Flag
O
When any valid byte applied to terminals B0-B35 fails parity,
PEFB
is LOW. Bytes are organized as B0-B8,
(Port B) B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. A byte is valid
when it is used by the bus size selected for Port B. The type of parity checked is determined by the state of
the ODD/EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB
LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the
PEFB
flag is forced HIGH regardless of the state of the B0-
B35 inputs.
PGA
Port A Parity
Generation
Port B Parity
Generation
Reset
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected
by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected
by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The
generated parity bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while
RST
is LOW. This sets the
AFA, AFB, MBF1,
and
MBF2
flags HIGH and the
EFA, EFB, AEA,
AEB, FFA,
and
FFB
flags LOW. The LOW-to-HIGH transition of
RST
latches the status of the FS1 and FS0
inputs to select Almost-Full and Almost-Empty flag offsets.
PGB
I
RST
I
SIZ0, SIZ1 Port B Bus
Size Selects
I
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and
BE,
and the following LOW-to-HIGH
(Port B) transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word,
word or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit write or
read.
I
At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by SW0
(Port B) and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping
is possible with any bus-size selection.
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
SW0, SW1 Port B Byte
Swap Select
W/RA
W/RB
Port A Write/
Read Select
Port B Write/
Read Select
5
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