74F377 Octal D-Type Flip-Flop with Clock Enable
April 1988
Revised September 2000
74F377
Octal D-Type Flip-Flop with Clock Enable
General Description
The 74F377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s
Ideal for addressable register applications
s
Clock enable for address and data synchronization
applications
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
See 74F273 for master reset version
s
See 74F373 for transparent latch version
s
See 74F374 for 3-STATE version
Ordering Code:
Order Number
74F377SC
74F377SJ
74F377PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009525
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74F377
Unit Loading/Fan Out
U.L.
Pin Names
D
0
–D
7
CE
CP
Q
0
–Q
7
Description
HIGH/LOW
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
Mode Select-Function Table
Inputs
Operating Mode
CP
Load “1”
Load “0”
Hold
(Do Nothing)
Output
D
n
h
I
X
X
Q
n
H
L
No Change
No Change
CE
I
I
h
H
X
H
=
HIGH Voltage Level
h
=
HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L
=
LOW Voltage Level
I
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F377
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
I
OS
I
CEX
V
ID
I
OD
I
CCH
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Output Short-Circuit Current
Output HIGH Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Power Supply Current
35
44
4.75
3.75
46
56
−60
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
−0.6
−150
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
mA
mA
µA
V
µA
mA
Min
Min
Min
Max
Max
Max
Max
Max
0.0
0.0
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
IN
=
0.5V
V
OUT
=
0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
CP
=
D
n
=
MR
=
HIGH
3
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74F377
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to Q
n
130
3.0
4.0
7.0
9.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
85
2.0
3.0
8.5
10.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
105
2.5
3.5
7.5
9.0
Max
MHz
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH to LOW
CE to CP
Clock Pulse Width,
HIGH or LOW
3.0
3.5
0.5
1.0
4.1
3.5
0.5
2.0
6.0
6.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
3.5
4.0
1.0
1.0
4.0
5.0
1.5
2.5
5.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.5
0.5
1.0
4.1
4.0
0.5
2.0
6.0
6.0
Max
ns
ns
ns
ns
ns
Units
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4
74F377
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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