Ordering number : ENA2304
LC87F0G08A
CMOS LSI
8-bit 1-chip Microcontroller
8K-byte Flash ROM / 256-byte RAM / 24-pin
Features
a 10
/20
amplifier
a 8/10-bit High-speed PWM(150kHz)
a Reference Voltage Generator Circuit(2V/4V) for an AD converter
a Temperature sensor
an internal reset circuit
a 7-channel AD converter with 12-/8-bit resolution selector
Internal oscillation circuits (30kHz/1MHz/8MHz)
http://onsemi.com
Performance
83.3ns (12.0MHz) VDD=2.7V to 5.5V Ta=
40C
to + 85C
125ns (8.0MHz) VDD=2.0V to 5.5V Ta=
40C
to + 85C
250ns (4.0MHz) VDD=1.8V to 5.5V Ta=
40C
to + 85C
SSOP24(225mil)
Function Descriptions
Ports
- I/O ports
: 18
- Reference voltage outputs : 1 (VREF)
- Power supply pins
: 3 (VSS1, VSS2, VDD1)
Timers (3ch)
- Timer 0 : 16-bit timer/counter with a capture register.
- Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
- a Base timer serving as a realtime clock
SIO (1ch)
- SIO1 : 8-bit asynchronous/synchronous serial interface
Comparator
Watchdog Timer
P70/INT0/T0LCP/AN09
RES
Frequency tunable 12-bit PWM
2ch
VSS1
CF1/XT1
System Clock Divider Function
CF2/XT2
CF Oscillation Circuit, X'tal Oscillation Circuit
VDD1
P10/SO1
15 sources, 10 vectors interrupts
P11/SI1/SB1
P12/SCK1
On-chip Debugger Function
P13/INT4/T1IN/AN7
P14/INT4/T1IN/AN6
P15/INT3/T0IN/AN5
1
2
3
4
5
6
7
8
9
10
11
12
LC87F0G08A
24
23
22
21
20
19
18
17
16
15
14
13
OWP0
P06/T1PWMH
P05/T1PWML /CKO
P04/AN4/VCPWM1
P03/AN3/VCPWM0
P02/AN2/CPIM
P01/APIP
P00/APIM
VREF
VSS2
P17/BUZ/INT1/T0HCP/HPWM2
P16/INT2/T0IN/CPOUT/HPWM2
Application
Shaver, Battery charge control
Pin Assignment (Top view)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of this data sheet.
Semiconductor Components Industries, LLC, 2014
March, 2014
Ver. 1.01
31014HKIM 20130905-S00003 No.A2304-1/31
LC87F0G08A
Function Details
Flash
ROM
Capable
of on-board programming with a wide range of supply voltages : 2.2 to 5.5V
Block-erasable
in 128 byte units
Writes
data in 2-byte units
8192
× 8 bits
RAM
256
× 9 bits
Bus
Cycle Time
83.3ns
( 12MHz, VDD=2.7V to 5.5V, Ta=40C to 85C)
125ns
( 8MHz, VDD=2.0V to 5.5V, Ta=40C to 85C)
250ns
( 4MHz, VDD=1.8V to 5.5V, Ta=40C to 85C)
Note : The bus cycle time here refers to the ROM read speed.
Minimum
Instruction Cycle Time (tCYC)
250ns
(12MHz, VDD=2.7V to 5.5V, Ta=40C to 85C)
375ns
( 8MHz, VDD=2.0V to 5.5V, Ta=40C to 85C)
750ns
( 4MHz, VDD=1,8V to 5.5V, Ta=40C to 85C)
Potrs
Normal withstand voltage I/O ports whose I/O direction can be designated in 1-bit units
18(P0n, P1n, P70, CF1, CF2)
Reset pins
1(RES)
Power supply pins
3(VSS1, VSS2,VDD1)
Reference voltage outputs
1(VREF)
Dedicated debugger port
1(OWP0)
Timers
Timer
0 : 16-bit timer/counter with 2 capture registers.
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3 : 16-bit counter (with two 16-bit capture registers)
Timer
1 : 16-bit timer/counter that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler
2 channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from lower-order 8 bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs)
(lower-order 8 bits may be used as a PWM output)
Base
timer
(1) The clock is selectable from the subclock (32.768kHz crystal oscillation), the low speed RC, system clock, and
timer 0 prescaler output.
(2) with an 8-bit programmable prescaler
(3) Interrupts programmable in 5 different time schemes
No.A2304-2/31
LC87F0G08A
SIO
SIO1
: 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
AD
Converter:
AD
converter input port with 10
/20
amplifier (1channel)
AD
converter input port (7channel)
12-/8-bit resolution selectable AD converter
Selectable
reference voltage source for an AD converter
( Selectable from VDD , Internal Reference Voltage Generator Circuit(VREF) .)
Internal
Reference Voltage Generator Circuit(VREF)
Generates
2.0V/4.0V for AD converter.
Comparator
Comparator input pin (1 channel)
Comparator output pin (1 channel)
Comparator output set high when (comparator input level) < 1.22V
Comparator output set low when (comparator input level) > 1.22V
Clock
Output Function
Generates
clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is
selected as the system clock.
Watchdog
Timer
Generates
an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock
(approx. 30kHz) or subclock.
Operating
mode at standby is selectable from 3 modes
(continue counting/suspend operation/suspend counting with the count value retained)
No.A2304-3/31
LC87F0G08A
Interrupts
15
sources, 10 vectors
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address is given priority.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/BT
T0H
T1L/T1H
HPWM2
SIO1
ADC
P0/VCPWM
Interrupt Source
Priority
levels X > H > L
Of
interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: Up to 128levels (the stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
16
bits
8 bits
(5 tCYC execution time)
24
bits
16 bits
(12 tCYC execution time)
16
bits
8 bits
(8 tCYC execution time)
24
bits
16 bits
(12 tCYC execution time)
Oscillation
Circuits
Internal
oscillation circuits
1) Low-speed RC oscillation circuit:
2) Medium-speed RC oscillation circuit:
3) Hi-speed RC oscillation circuit1:
4) Hi-speed RC oscillation circuit2:
For system clock (approx.30kHz)
For system clock (1MHz)
For system clock (8MHz)
For High speed PWM (40MHz)
System
Clock Divider Function
Can
run on low consumption current.
Minimum
instruction cycle selectable from 375ns, 750ns, 1.5s, 3.0s, 6.0s, 12.0s, 24.0s, 48.0s, and
96.0s (at 8MHz main clock)
Internal
Reset Circuit
Power-on
reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level is 1.67V.
Low-voltage
detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level can be selected from 7 levels
(1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V and 4.28V), through option configuration.
No.A2304-4/31
LC87F0G08A
Standby
Function
●
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt generated
●
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC and crystal oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
2) There are four ways of resetting the HOLD mode:
(1) Setting the reset pin to the lower level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt source established at one of the INT0, INT1, INT2 and INT4 pins
* INT0 and INT1 can be used in the level sense mode only.
(4) Having an interrupt source established at port 0.
●
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(when X’tal oscillation or low-speed RC oscillation is selected).
1) The CF, low-speed, and medium-speed RC oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
Note: If the base timer is run with low-speed RC oscillation selected as the base timer input clock source and the
X’tal HOLD mode is entered, the low-speed RC oscillator retains the state that is established when the
X’tal HOLD mode is entered.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt source established at one of the INT0, INT1, INT2, and INT4 pins
* INT0 and INT1 can be used in the level sense mode only.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
VCPWM:
Frequency tunable 12-bit PWM × 2ch
High
speed PWM (HPWM2)
8-/10- bits PWM ×1ch
1) The PWM clock is selectable from system clock and Hi-speed RC2 (40MHz)
2) The PWM type is selectable from 8 bits(Normal mode) and 10 bits(
additive
puls mode).
Temperature
sensor
Senseor
voltage can be comapred by the AD converter.
On-chip
Debugger Function
Supports
software debugging with the IC mounted on the target board.
Provides
1 channel of on-chip debugger pin.
OWP0
Data
Security Function
Protects
the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Package
Form
SSOP24
(225mil): Lead-free and halogen-free type
No.A2304-5/31
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