DUAL CMOS SyncFIFO™
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841/72851
Separate control lines and data lines for each FIFO
Separate Empty, Full, Programmable Almost-Empty and Almost-
Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
DESCRIPTION:
The IDT72801/72811/72821/72831/72841/72851 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control, data, and flag lines assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0
- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each
input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write
Enable pins (WENA1, WENA2,
WENB1,
WENB2). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate write enable pins are asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1,
RENA2, RENB1,
RENB2).
The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA,
OEB)
is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (EFA,
EFB)
and Full (FFA,
FFB).
Two programmable flags, Almost-Empty (PAEA,
PAEB)
and Almost-Full
(PAFA,
PAFB),
are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to empty+7 for
PAEA
and
PAEB,
and full-7 for
PAFA
and
PAFB.
The IDT72801/72811/72821/72831/72841/72851 architecture lends itself
to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
These FIFOs is fabricated using high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA0 - DA8
EFA
PAEA
PAFA
LDA
FFA
WCLKB
WENB1
WENB2
DB0 - DB8
LDB
INPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
INPUT REGISTER
OFFSET REGISTER
EFB
PAEB
PAFB
FFB
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RESET LOGIC
OUTPUT REGISTER
RSA
OEA
QA0 - QA8
RCLKA
RENA1
RENA2
RSB
OEB
QB0 - QB8
RCLKB
RENB1
RENB2
3034 drw 01
IDT, IDT logo and the
SyncFIFO
logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
©2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2018
DSC-3034/7
1
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
QA
0
FFA
EFA
OEA
RENA2
RCLKA
RENA1
GND
QB
8
QB
7
QB
6
QB
5
QB
4
QB
3
QB
2
QB
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DA
5
DA
4
DA
3
DA
2
DA
1
DA
0
PAFA
PAEA
WENB2/LDB
WCLKB
WENB1
RSB
DB
8
DB
7
DB
6
DB
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
QA
1
QA
2
QA
3
QA
4
QA
5
QA
6
QA
7
QA
8
V
CC
WENA2/LDA
WCLKA
WENA1
RSA
DA
8
DA
7
DA
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QB0
FFB
EFB
OEB
RENB2
RCLKB
RENB1
GND
V
CC
PAEB
PAFB
DB
0
DB
1
DB
2
DB
3
DB
4
3034 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
MARCH 2013
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred
to as FIFO A and FIFO B, are identical in every respect. The following
Symbol
DA0-DA8
DB0-DB8
RSA
,
RSB
Name
A Data Inputs
B Data Inputs
Reset
I/O
I
I
I
description defines the input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
Description
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When
RSA
(
RSB
) is set LOW, the associated internal read and write pointers of array A (B) are set to
the first location;
FFA
(
FFB
) and
PAFA
(
PAFB
) go HIGH, and
PAEA
(
PAEB
) and
EFA
(
EFB
) go
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
enable(s) are asserted.
If FIFO A (B) is configured to have programmable flags,
WENA1
(
WENB1
) is the only Write
Enable pin that can be used. When
WENA1
(
WENB1
) is LOW, data A (B) is written into the FIFO
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1
(
WENB1
) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if
FFA
(
FFB
) is LOW.
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If
LDA
(
LDB
)
is HIGH at reset, this pin operates as a second write enable. If WENA2/
LDA
(WENB2/
LDB
) is LOW
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables,
WENA1
(
WENB1
) must be LOW
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if
FFA
(
FFB
) is LOW. If the FIFO is configured to have programmable flags,
LDA
(
LDB
) is held LOW to write or
read the programmable flag offsets.
9-bit data outputs from RAM array A.
9-bit data outputs from RAM array B.
Data is read from FIFO A (B) on a
LOW
-to-
HIGH
transition of RCLKA (RCLKB) when
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are asserted.
When
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are LOW, data is read from FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if
EFA
(
EFB
) is LOW.
When
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are LOW, data is read from the FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the
EFA
(EFB) is LOW.
When
OEA
(
OEB
) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If
OEA
(
OEB
) is HIGH, the
outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state.
When
EFA
(
EFB
) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
When
EFA
(
EFB
) is HIGH, FIFO A (B) is not empty.
EFA
(
EFB
) is synchronized to RCLKA (RCLKB).
When
PAEA
(
PAEB
) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
appropriate offset register. The default offset at reset is Empty+7.
PAEA
(
PAEB
) is synchronized to
RCLKA (RCLKB).
When
PAFA
(
PAFB
) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
offset register. The default offset at reset is Full-7.
PAFA
(
PAFB
) is synchronized to WCLKA (WCLKB).
When
FFA
(
FFB
) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
When
FFA
(
FFB
) is HIGH, FIFO A (B) is not full.
FFA
(
FFB
) is synchronized to WCLKA (WCLKB).
+5V power supply pin.
0V ground pin.
WCLKA
WCLKB
WENA1
WENB1
Write Clock
Write Enable 1
I
I
WENA2/
LDA
WENB2/
LDB
Write Enable 2/
Load
I
QA0-QA8
QB0-QB8
RCLKA
RCLKB
RENA1
RENB1
RENA2
RENB2
OEA
OEB
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
A Data Outputs
B Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
O
O
I
I
I
I
O
O
O
O
VCC
GND
3
MARCH 2013
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Com'l & Ind'l
Unit
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
Min.
Typ.
Max. Unit
Terminal Voltage with
Respect to GND
Storage
Temperature
DC Output
Current
–0.5 to +7.0
–55 to +125
–50 to +50
V
°
C
mA
V
CC
GND
V
IH
V
IL
T
A
T
A
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply Voltage
(Com'l & Ind'l)
Supply Voltage
(Com'l & Ind'l)
Input High Voltage
(Com'l & Ind'l)
Input Low Voltage
(Com'l & Ind'l)
Operating Temperature
Commercial
Operating Temperature
Industrial
4.5
0
2.0
—
0
–40
5.0
0
—
—
—
—
5.5
0
—
V
V
V
0.8 V
70
°C
85
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C)
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
Commercial and Industrial
(1)
t
CLK
= 10, 15, 25 ns
IDT72851
Commercial and Industrial
(1)
t
CLK
= 10, 15, 25 ns
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6,8)
I
CC2(
4,7,8
)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current (both FIFOs)
Standby Current
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
60
10
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
80
10
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs open (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
CC1
= 2*[1.7 + 0.7*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 5V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
°
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
8. I
CC1
and I
CC2
parameters are improved as compared to previous data sheets.
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
NOTE:
1. With output deselected (OEA,
OEB
≥
V
IH
).
2. Characterized values, not currently tested.
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
4
MARCH 2013
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C)
Com'l &
Commercial
IDT72801L10
IDT72811L10
IDT72821L10
IDT72831L10
IDT72841L10
IDT72851L10
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable
Almost-Full Flag
Read Clock to Programmable
Almost-Empty Flag
Skew Time Between Read Clock and
Write Clock for Empty Flag and Full Flag
Skew Time Between Read Clock and Write
Clock for Programmable Almost-Empty Flag
and Programmable Almost-Full Flag
Min
—
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
—
0
3
3
—
—
—
—
5
14
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
10
—
6
6
6.5
6.5
6.5
6.5
—
—
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
6
15
IDT72801L15
IDT72811L15
IDT72821L15
IDT72831L15
IDT72841L15
IDT72851L15
Min
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
—
2
25
10
10
6
1
6
1
15
15
15
—
0
3
3
—
—
—
—
10
18
Ind'l
(1)
IDT72801L25
IDT72811L25
IDT72821L25
IDT72831L25
IDT72841L25
IDT72851L25
Min
Max.
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
D.U.T.
680Ω
30pF*
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
1.5V
See Figure 1
or equivalent circuit
3034 drw 03
Figure 1. Output Load
*Includes jig and scope capacitances.
5
MARCH 2013
FPGA/CPLD
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