Si53360/61/62/65 Data Sheet
Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputs
and Frequency Range from dc to 200 MHz
The Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distribu-
tion and redundant clocking applications. The family utilizes Silicon Labs advanced
CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive
jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR
performance and eliminates the need for external components simplifying low jitter
clock distribution in noisy environments.
The CMOS buffers are available in multiple configurations with 8 outputs
(Si53360/61/65), or dual banks of 6 outputs each (Si53362). These buffers can be
paired with the Si534x clock generators and Si5xx oscillators to deliver end-to-end
clock tree performance.
KEY FEATURES
• Low additive jitter: 120 fs rms
• Built-in LDOs for high PSRR performance
• Up to 12 LVCMOS Outputs from LVCMOS
inputs
• Frequency range: dc to 200 MHz
• Multiple configuration options
• Dual Bank option
• 2:1 Input MUX option
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply
Filtering
8
CLK0
0
VDDOA
CLK1
CLK_SEL
6
6 Outputs
OEB
VDDOB
1
6
OEA
6 Outputs
Si53362
CLK
8
8 Outputs
VDDO (Si53361 only)
OEA
8 Outputs
Si53360/61
VDD
Power Supply
Filtering
OE
Si53365
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Si53360/61/62/65 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si5336x Ordering Guide
Part Number
Si53360-B-GT
Si53361-B-GM
Si53362-B-GM
SI53365-B-GT
Input
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
LVCMOS
1 bank / 1 Input
LVCMOS
LVCMOS Output
1 bank / 8 Outputs
1 bank / 8 Outputs
(Settable VDDO)
2 banks / 6 Outputs
1 bank / 8 Outputs
Output Enable
Single
Single
1 per bank
Single
Frequency Range
dc to 200 MHz
dc to 200 MHz
dc to 200 MHz
dc to 200 MHz
Package
16-TSSOP
16-QFN
3x3 mm
24-QFN
4x4 mm
16-TSSOP
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Si53360/61/62/65 Data Sheet
Functional Description
2. Functional Description
The Si53360/61/62/65 are a family of low-jitter, low skew, fixed format (LVMCOS) buffers. These devices are available in multiple con-
figurations customized for the end application (refer to
1. Ordering Guide
for more details on configurations).
2.1 LVCMOS Input Termination
The table below summarizes the various ac- and dc-coupling options supported by the LVCMOS device, and the figure shows the rec-
ommended input clock termination.
Table 2.1. LVCMOS Input Clock Options
LVCMOS
AC-Coupled
1.8 V
2.5/3.3 V
No
Yes
DC-Coupled
Yes
Yes
V
DD
V
DD
= 3.3 V, 2.5 V, or 1.8 V
CMOS
Driver
Rs
50
CLKx
Si53360/61/62/65
Note:
Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace.
Figure 2.1. Recommended Input Clock Termination
2.2 Input Mux
The Si53360-61/62 provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin
selects the active clock input. The following table summarizes the input and output clock based on the input mux settings.
Table 2.2. Input Mux Logic
CLK_SEL
L
L
H
H
CLK0
L
H
X
X
CLK1
X
X
L
H
Q
L
H
L
H
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Si53360/61/62/65 Data Sheet
Functional Description
2.3 Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs should be left unconnected.
VDD
Si5336x
Zout
Rs
Zo
50
CMOS
Receivers
Note:
Rs = 33 ohm for 3.3 V and 2.5 V operation.
Rs = 0 ohm for 1.8 V operation.
Figure 2.2. LVCMOS Output Termination
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Si53360/61/62/65 Data Sheet
Functional Description
2.4 AC Timing Waveforms
T
PHL
CLK
Q
T
PLH
Propagation Delay
VPP/2
T
SK
Q
N
Q
M
T
SK
Output-Output Skew
VPP/2
VPP/2
VPP/2
T
F
Q
80% VPP
20% VPP
Q
T
R
80% VPP
20% VPP
Rise/Fall Time
Figure 2.3. AC Timing Waveforms
2.5 Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world envi-
ronments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements.
See “AN491:
Power Supply Rejection for Low-Jitter Clocks”
for more information.
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