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Rev. 11-18-04
Page 2
SMSC LAN91C113
DATASHEET
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
5.1
5.2
6.1
6.2
6.3
6.4
6.5
General Description ............................................................................................................. 7
MII Disable..............................................................................................................................................26
Figure 3.3 - LAN91C113 Physical Layer to Internal Mac Block Diagram .....................................................................12
Figure 6.1 - MI Serial Port Frame Timing Diagram.......................................................................................................22
Figure 6.2 - MII Frame Format & MII Nibble Order.......................................................................................................23
Figure 6.3 - TX/10BT Frame Format ............................................................................................................................25
Figure 6.6 - SOI Outage Voltage Template – 10MBPS................................................................................................36
Figure 6.7 - Link Pulse Output Voltage Template – NLP, FLP .....................................................................................37
Figure 6.8 - NLP VS. FLP Link Pulse ...........................................................................................................................38
Figure 7.1 - Data Frame Format...................................................................................................................................43
Figure 9.4 - TXEMPTY INTR (Assumes Auto Release Option Selected).....................................................................85
Figure 9.5 – Drive Send and Allocate Routines............................................................................................................86
Figure 9.6 – Interrupt Generation for Transmit, Receive, MMU....................................................................................88
Figure 10.1 - 64 X 16 Serial EEPROM Map .................................................................................................................91
Figure 11.1 - LAN91C113 on VL Bus ...........................................................................................................................93
Figure 11.2 - LAN91C113 on ISA Bus .........................................................................................................................95
Figure 11.3 - LAN91C113 On EISA Bus ......................................................................................................................97
Figure 13.4 – Address Latching for all Modes ............................................................................................................106
Figure 13.12 – Jam Timing.........................................................................................................................................114
Figure 13.13 – Link Pulse Timing...............................................................................................................................116
Figure 13.14 - FLP Link Pulse Timing ........................................................................................................................117
许多MEMS器件，像加速度计、机械共振器件等，都需要在真空环境下才能实现设计功能。然而检验封装腔体是否达到了所要求的真空程度一直一来都是个棘手的问题。密歇根大学Khalil Najafi教授研究小组的研究人员最近开发出一种用微机械制造方法实现，可以在封装的封帽上完成皮拉尼真空测量的方案。使用这种方法可以完成封装的氦气检漏测试，该成果已发表在IEEE Transactions on Advan...[详细]
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