S i 5 1 0 0 / Si 5 11 0 - E VB
E v a l u a t i o n B o a r d S e t f o r S i 5 1 0 0 a n d S i 5 11 0
OC-48/STM-16 SONET/SDH T
RANSCEIVERS
Description
The Si5100-EVB and Si5110-EVB motherboard/
daughter card sets provide a platform for testing and
characterizing Silicon Laboratories’ Si5100/Si5110
SiPHY
TM
OC-48/STM-16 SONET/SDH Transceiver.
The Si5100 and Si5110 transceiver devices provide full-
duplex operation at serial data rates up to 2.7 Gbps.
The transceiver device is mounted on the EVB daughter
card. The high-speed serial signals are accessed via
SMA connectors on the daughter card itself. The low-
speed parallel data channels are routed from the
daughter card to the motherboard through the industry-
standard 300-pin meg-array connector.
The included transceiver loopback motherboard
provides a hardware connection between the
transceiver low-speed parallel data outputs, RXDOUT,
and the transceiver low-speed parallel data inputs,
TXDIN. Test points are provided on the motherboard to
allow monitoring of the parallel data channels. The clock
signals associated with the low-speed data channels
are routed to SMA connectors on the loopback
motherboard. Static control and status signals are
routed to standard 100-mil center posts.
An optional full-duplex motherboard is also available for
the transceiver daughter card. The full-duplex
motherboard also utilizes the industry-standard 300-pin
meg-array connector to allow attachment of the
daughter card. The full-duplex motherboard routes all of
the transceiver low-speed parallel data outputs and
inputs to standard SMA connectors. The optional full-
duplex motherboard is useful when connecting the
transceiver device to a parallel bit error rate tester
(ParBERT), or in other applications that require full
access to the low-speed parallel data channels.
Features
Separate supply connections for VDD (1.8 V) and
VDDIO (1.8 V or 3.3 V) allow LVTTL I/Os to be
powered at either 1.8 V or 3.3 V.
Control inputs are jumper configurable.
Status outputs brought out to headers for easy
access.
Potentiometers provided for controlling analog
inputs.
Loopback Motherboard (included) provides
hardware path between low-speed parallel data
outputs RXDOUT and low-speed parallel data inputs
TXDIN.
Optional full-duplex motherboard provides access to
all low-speed parallel data outputs and inputs via
SMA connectors.
Preliminary Rev. 0.5 6/03
Copyright © 2003 by Silicon Laboratories
Si5100/Si5110-EVB-05
Si5100/Si5110-EVB
Functional Description
The Si5100-EVB and Si5110-EVB motherboard and
daughter card sets simplify characterization of the OC-
48/STM-16 and FEC transceiver devices by providing
convenient access to the device I/Os. Device
performance can be evaluated in various modes by
following the “Basic Test Setup” section.
Data I/O Signals
The serial 2.5 Gbps data and 2.5 GHz clock paths are
routed as coplanar differentially-coupled microstrip
transmission lines on the daughter card. These three
signals (RXDIN, TXCLKOUT, and TXDOUT) are ac
coupled to standard SMA jacks for ease in connection
to industry standard test equipment. Take care when
connecting cables to these jacks. Use a standard SMA
torque wrench to minimize reflections at the cable-to-
jack interface. Finally, match all differential connections
in length to minimize phase differences between the
positive and negative terminals.
Power Supply
The transceiver device can be powered from a single
1.8 V supply or seperate 1.8 V and 3.3 V supplies.
When the additional 3.3 V supply is applied, the status
outputs are LVTTL compatible. The daughter card can
be configured for either mode of operation by setting the
VDD_IO SEL jumper as shown in Figure 4.
Differential Parallel Data and
Clock I/O Signals
The differential parallel data lines are routed through the
300-pin meg-array connector to the motherboard. The
standard loopback motherboard directly couples the
RXDOUT bus to the TXDIN bus. The optional full-
duplex motherboard directly couples the RXDOUT and
TXDIN buses to standard SMA jacks for connection to
industry standard test equipment.
For 3.3 V/1.8 V operation
1.8 V
VDD_IO
SEL
3.3 V
For 1.8 V operation only
VDD_IO
SEL
1.8 V
Slice Level, Loss-of-Signal Level, and
Phase Adjust
Voltages present at the Slice Level (SLICELVL), Loss-
of-Signal Level (LOSLVL) and Phase Adjust
(PHASEADJ) pins can be used to adjust the data slicing
level, the loss-of-signal alarm level, and the sampling
phase position, respectively. Because these inputs are
high impedance, simple turn-based potentiometers are
used to apply the control voltage. The Si5100-EVB
provides 50 k potentiometers for each of these inputs:
potentiometer R16 sets the voltage applied to the
SLICELVL pin; R14 sets the voltage applied to the
LOSLVL pin, and R15 sets the voltage applied to the
PHASEADJ pin. The Si5110-EVB also provides 50 k
potentiometers for each of these inputs. Potentiometer
R5 sets the voltage applied to the SLICELVL pin; R3
sets the voltage applied to the LOSLVL pin, and R4 sets
the voltage applied to the PHASEADJ pin. The
potentiometers are connected so the voltage applied
varies from GND to VREF. Refer to the device data
sheet for details on the operation of these inputs.
3.3 V
Figure 4. VDD_IO Selection Jumpers
Control Inputs
The device control inputs are located on the
motherboard and daughter card. Signals with equivalent
module functions are routed to the motherboard header,
JP1. Signals specific to the transceiver are routed on
the daughter card to jumpers JP1 and JP2. In both
cases, the signal is routed to the center pin of a three
pin group where the adjacent pins are power and
ground. The device inputs are pulled high or low so that
leaving a signal unconnected will not harm the device.
Status Outputs
The device status outputs are located on the
motherboard and daughter card. Signals with equivalent
module functions are routed to the motherboard header,
JP2. Signals specific to the transceiver are routed on
the daughter card to headers JP3 and JP4. In both
cases, the signal is routed to a header pin adjacent to a
ground pin.
Basic Test Setup
The configurations listed in Tables 1 and 3 allow easy
setup of the transceiver evaluation system for operation
in the line loopback, full duplex, or diagnostic loopback
modes. Other configurations are supported; however,
operation should first be verified in one of these modes
in order to minimize the number of unknown variables.
Rev. 0.5
5
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