DATASHEET
HIP2103, HIP2104
60V, 1A/2A Peak, Half Bridge Driver with 4V UVLO
The HIP2103 and HIP2104 are half bridge drivers designed for
applications using DC motors, three-phase brushless DC
motors, or other similar loads.
Two inputs (HI and LI) are provided to independently control
the high side driver (HO) and the low side driver (LO).
Furthermore, the two inputs can be configured to
enable/disable the device, thus lowering the number of
connections to a microcontroller and lowering costs.
The very low IDD bias current in the Sleep Mode prevents
battery drain when the device is not in use, thus eliminating
the need for an external switch to disconnect the driver from
the battery.
A fail-safe mechanism is included to improve system reliability
and to minimize the possibility of catastrophic bridge failures
due to controller malfunction. Internal logic prevents both
outputs from turning on simultaneously when HI and LI are
both high simultaneously. Dead-time is still required on the
rising edge of the HI (or LI) input when the LI (or HI) input
transitions low.
Integrated pull-down resistors on all of the inputs (LI, HI, VDen
and VCen) reduces the need for external resistors. An active
low resistance pull-down on the LO output ensures that the low
side bridge FET remains off during the Sleep Mode or when
VDD is below the undervoltage lockout (UVLO) threshold.
The HIP2104 has a 12V linear regulator and a 3.3V linear
regulator with separate enable pins. The 12V regulator
provides internal bias for VDD and the 3.3V regulator provides
bias for an external microcontroller (and/or other low voltage
ICs), thus eliminating the need for discrete LDOs or DC/DC
converters.
The HIP2103 is available in a 3x3mm, 8 Ld TDFN package and
the HIP2104 is available in a 4x4mm, 12 Ld DFN package.
FN8276
Rev 0.00
November 27, 2013
Features
• 60V maximum bootstrap supply voltage
• 3.3V and 12V LDOs with dedicated enable pins (HIP2104)
• 5µA sleep mode quiescent current
• 4V undervoltage lockout
• 3.3V or 5V CMOS compatible inputs with hysteresis
• Integrated bootstrap FET (replaces traditional boot strap diode)
Applications
• Half bridge, full bridge and BLDC motor drives
(see Figures 21, 22, 23)
• UPS and inverters
• Class-D amplifiers
• Any switch mode power circuit requiring a half bridge driver
Related Literature
•
AN1896
“HIP2103, HIP2104 Evaluation Board User’s Guide”
•
AN1899
“HIP2103, HIP2104 3-phase, Full or Half Bridge
Motor Drive User’s Guide”
VBAT
VBAT
VBAT
VCen
VCC
VDD
HB
HB
VDD
HO
HI
LI
HO
HI
HS
LO
DC
MOTOR
HS
LO
VDD
5.5
5.0
4.5
I
BAT
(µA)
4.0
3.5
3.0
2.5
EPAD
VDen
HIP2104
HIP2103
LI
µController
VSS
VSS
EPAD
2.0
10
20
30
V
BAT
(VDC)
40
50
FIGURE 1. TYPICAL FULL BRIDGE APPLICATION
FIGURE 2. HIP2104 SHUTDOWN CURRENT vs V
BAT
FN8276 Rev 0.00
November 27, 2013
Page 1 of 21
HIP2103, HIP2104
Block Diagram
VBAT
VCC
3.3V LDO
155C
OT
12V LDO
VDD
VCen
100k
1 MSEC
DELAY
1 MSEC
DELAY
VDen
100K
2104
2103
VBAT
4V
UNDER
VOLTAGE
2103
2104
Boot FET
20 US
DELAY
R
20 US
DELAY
Q
SLEEP
MODE
1
SEE FIGURES 3 AND 4 FOR
SLEEP MODE TIMING DETAILS
HB
VDD
LOGIC
BIAS
S
HI
LEVEL
SHIFT
4V
UNDER
VOLTAGE
2M
HO
100k
E
P
A
D
LI
Logic prevents
shoot-through
when LI and HI
are both high
HS
VDD
LO
Active pull-down
keeps bridge FET
off during UV, OT,
or sleep
100
100k
VSS
Symbol Glossary
10 US
DELAY
Time delay functional block with
rising edge prop delay (as indicated
by the rising arrow on the input) and
minimal falling edge delay.
2104
2103
Optional connections as indicated by
part numbers
HIP2103
HIP2104
FN8276 Rev 0.00
November 27, 2013
Page 2 of 21
HIP2103, HIP2104
Pin Configurations
HIP2103
(8 LD 3x3 TDFN)
TOP VIEW
VDD
HI
LI
VSS
1
2
3
4
8
7
6
5
HB
HO
HS
LO
VDen
VCen
VCC
VDD
HI
LI
1
2
3
4
5
6
EPAD
(VSS)
HIP2104
(12 LD 4x4 DFN)
TOP VIEW
12
11
10
9
8
7
VBAT
HB
HO
HS
LO
VSS
EPAD
(VSS)
Pin Descriptions
HIP2103
8 LD
TDFN
-
-
-
1
2
3
4
5
6
7
8
-
EP
HIP2104
12 LD
DFN
1
2
3
4
5
6
7
8
9
10
11
12
EP
SYMBOL
VDen
VCen
VCC
VDD
HI
LI
VSS
LO
HS
HO
HB
VBAT
EPAD
DESCRIPTION
(HIP2104 only) VDD enable input, 3.3V or 5V logic compatible, V
BAT
tolerant. VDD output is turned on after
1ms debouncing period.
(HIP2104 only) VCC enable input, 3.3V or 5V logic compatible. V
BAT
tolerant. VCC output is turned on after
1ms debouncing period.
(HIP2104 only) 3.3V output voltage of linear regulator, 75mA. Enabled by VCen.
(HIP2103) Input voltage 14V max.
(HIP2104) 0utput voltage of linear regulator, 12V nominal, 75mA. Enabled by VDen.
High side input, 3.3V or 5V logic compatible. (HI -> HO).
Low side Input, 3.3V or 5V logic compatible. (LI -> LO).
Signal ground.
Low side driver Output. (LI ->LO).
High side FET Source connection (low side boot capacitor connection).
High side driver Output. (HI -> HO)
High side Boot capacitor.
(HIP2104 only) Positive battery (bridge voltage) connection.
Exposed Pad, must be connected to signal ground.
FN8276 Rev 0.00
November 27, 2013
Page 3 of 21
HIP2103, HIP2104
Ordering Information
PART NUMBER
(Notes 1, 2, 3, 4)
HIP2103FRTAAZ
HIP2104FRAANZ
HIP2103-4DEMO1Z
HIP2103_4MBEVAL1Z
NOTES:
1. Add “-T*”, suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
HIP2103, HIP2104.
For more information on MSL, please see Technical
Brief
TB363.
4. All part numbers are rated -40°C to +125°C for the recommended operating junction temperature range.
PART
MARKING
DZBF
2104AN
UVLO
(V)
4.0
4.0
VCC
REGULATOR
(V)
N/A
3.3
VDD
REGULATOR
(V)
N/A
12
PACKAGE
(Pb-Free)
8 Ld 3x3 TDFN
12 Ld 4x4 DFN
PKG.
DWG. #
L8.3x3A
L12.4x4A
HIP2103, HIP2104 3-phase, Full, or Half Bridge Motor Drive Demonstration Board
HIP2103, HIP2104 Evaluation Board
FN8276 Rev 0.00
November 27, 2013
Page 4 of 21
HIP2103, HIP2104
Absolute Maximum Ratings
(Note 5)
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld DFN Package (Notes 7, 8). . . . . . . . . .
46
7
12 Ld TDFN Package (Notes 7, 8) . . . . . . .
44
7
Max Power Dissipation at +25°C in free air
8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3W
12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2W
Max Power Dissipation at +25°C on copper plane
8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W
12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Operating Junction Temperature Range. . . . . . -40°C to +150°C
Nominal Over Temperature Shut-down . . . . . . . . . . . . . . . . . . . . . . .+155°C
Over Temperature Shut-down Range . . . . . . . . . . . . . . . +145°C to +165°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Supply Voltage V
DD
(HIP2103 only) . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Bridge Supply Voltage V
BAT
(HIP2104 Only) . . . . . . . . . . . . . . . -0.3V to 60V
High side Bias Voltage (V
HB -
V
HS)
(Note 10). . . . . . . . . . . . . . . -0.3V to 16V
Logic Inputs VCen, VDen (HIP2104 Only) . . . . . . . . . . - 0.3v to V
BAT
+ 0.3V
Logic Inputs LI, HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to V
DD
+ 0.3V
Output Voltage LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to V
DD
+ 0.3V
Output Voltage HO . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
- 0.3V to V
HB
+ 0.3V
Voltage on HS (Note 9, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10V to 60V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
HS
- 0.3V to 66V
Average Current in Boot Diode (Note 6). . . . . . . . . . . . . . . . . . . . . . . 100mA
Maximum Boot Cap Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µF
Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . . . . . 200mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up (Tested per JESD-78B; Class 2, Level A) all pins. . . . . . . . 100mA
Recommended Operating Conditions
(Note 5)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, V
BAT
(HIP2104 only) (Note 11). . . . . . . . . . . . . 5.0V to 50V
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
High Side Bias Voltage (V
HB -
V
HS)
(Note 10) . . . . . . . . . . . . . . -0.3V to 14V
Voltage on HS, Continuous, V
HS
(Notes 9, 10) . . . . . . . . . . . . . .-10V to 50V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
- 0.3V to 60V
Logic Inputs VCen, VDen (HIP2104 only). . . . . . . . . . . . . . . . . . . .0V to V
BAT
Output Voltage (LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V
DD
Output Voltage (HO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
to V
HB
Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . 0 to 150mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. All voltages are referenced toVSS unless otherwise specified.
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by trans conductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, the maximum output current must be limited by external means to less than the specified
recommended rectified average output current.
7.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
9. The the maximum value of V
HS
must be limited so that V
HB
does not exceed 60V.
10. The -10V limit for V
HS
has no time duration restrictions as far as the HS pin is concerned however, be aware that if the duration of the negative voltage
is significant with respect to the time constant to charge the boot capacitor (across HB and HS) the voltage on the boot capacitor can charge as high
as V
DD
- (-V
HS
) = (V
DD
+V
HS
) potentially violating the Voltage Rating for (V
HB -
V
HS).
11. When V
BAT
< ~13V, the output of VDD will sag. The 5V minimum specified for V
BAT
is the minimum level for which the UVLO will not activate.
DC Electrical Specifications
V
DD
= V
HB
= 12V (for HIP2103), V
SS
= V
HS
= 0V, V
BAT
= 18V (for HIP2104), LI = HI = 0V. No load on HO
and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T
J
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
J
= -40°C to +125°C
MIN
(Note 12)
MAX
(Note 12)
UNITS
LINEAR BIAS SUPPLIES (HIP2104 only)
V
DD
Output Voltage Over Rated
Line, Load, and Temperature
V
DD
Rated Output Current
V
DD
Output Current Limit
(brick wall)
V
DD
Drop Output Voltage
(Figure 7)
V
DD12
I
DDR
I
DD12
VDdout
Load = 75mA
83
151
237
Nominal V
DD
= 12V
-2.5
+2.1
+4.8
75
80
0.06
245
0.7
- 5%
+ 5%
%
mA
mA
V
FN8276 Rev 0.00
November 27, 2013
Page 5 of 21
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
