Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
(Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (B
JA
) .......83.9NC/W
Junction-to-Case Thermal Resistance (B
JC
) ...............37NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
CC
= 3.0V to 5.5V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 5.0V and T
A
= +25NC.) (Note 2)
PARAMETER
POWER SUPPLY
V
CC
Supply Voltage
V
CC
CB0 = high
CB0 = low (Note 3)
CB1 = CB0 = low (AM2
mode)
MAX14641–
MAX14644
CB1 = CB0 = high (CM
mode)
CB1 = low, CB0 = high
(PM mode)
MODE_SEL[2:0] = 000
(AM2 mode)
MAX14640/
MAX14651
MODE_SEL[2:0] = 011
(CM mode)
MODE_SEL[2:0] = 001
(PM mode)
POR Delay
Analog Signal Range
TDP/TDM On Resistance
TDP/TDM On-Resistance
Matching Between Channels
TDP/TDM On-Resistance
Flatness
DP/DM Short On-Resistance
t
POR
V
DP
, V
DM
R
ON
DR
ON
R
FLAT
R
SHORT
(Note 4)
V
IN
= 0V to V
CC
, I
IN
= 10mA
V
CC
= 5.0V, I
IN
= 10mA, V
IN
= 0.4V
V
CC
= 5.0V, I
IN
= 10mA, V
IN
= 0V to V
CC
V
DP
= 1V, R
L
= 20kI on DM
0
3.5
0.1
0.1
70
128
50
V
CC
6.5
ANALOG SWITCHES (DP, DM, TDP, TDM)
V
I
I
I
I
3.0
4.75
5.5
5.25
200
100
20
FA
200
100
20
ms
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Current
I
CC
www.maximintegrated.com
Maxim Integrated
│
2
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Electrical Characteristics (continued)
(V
CC
= 3.0V to 5.5V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 5.0V and T
A
= +25NC.) (Note 2)
PARAMETER
Off Leakage Current
On Leakage Current
DYNAMIC PERFORMANCE
Turn-On Time
Turn-Off Time
TDP/TDM Propagation Delay
DP/DM Output Skew
DP/DM On-Capacitance
(Connected to TDP, TDM)
Bandwidth
Off-Isolation
Crosstalk
DCP INTERNAL RESISTORS
DP/DM Short Pulldown
RP1/RP2 Ratio
RP1 + RP2 Resistance
RM1/RM2 Ratio
RM1 + RM2 Resistance
RSS1/RSS2 Ratio
RSS1 + RSS2 Resistance
CDP INTERNAL RESISTORS
DP Pulldown Resistor
DM Pulldown Resistor
Threshold Voltage
V
DM_SRC
Voltage
R
DP_CDP
R
DM_CDP
V
TH_CDP
V
DM_SRC
I
LOAD
= 0 to 200FA
CDP mode
CDP mode
14.25
14.25
100
0.5
19.53
19.53
161
24.80
24.8
205
0.7
kI
kI
mV
V
R
PD
RT
RP
R
RP
RT
RM
R
RM
RT
RSS
R
RSS
320
1.485
92
0.844
68
2.9
30
500
1.5
125
0.85
93
3
40
700
1.515
158.5
0.864
118
3.1
60
kI
kI
kI
kI
t
ON
t
OFF
t
PHL
, t
PLH
t
SKEW
C
OFF
BW
V
ISO
V
CT
V
TDP
or V
TDM
= 1.5V, R
L
= 300I,
C
L
= 35pF, Figure 1 (Note 4)
V
TDP
or V
TDM
= 1.5V, R
L
= 300I,
C
L
= 35pF, Figure 1 (Note 4)
R
L
= R
S
= 50I, DP and DM connected to
TDP and TDM, Figure 2
R
L
= R
S
= 50I, DP and DM connected to
TDP and TDM, Figure 2
f = 240MHz, V
BIAS
= 0V, V
IN
= 500mV
P-P
R
L
= R
S
= 50I, Figure 3
V
IN
= 0dBm, R
L
= R
S
= 50I, f = 250MHz,
Figure 3
V
IN
= 0dBm, R
L
= R
S
= 50I, f = 250MHz,
Figure 3
20
1
60
40
5
1000
-20
-25
Fs
Fs
ps
ps
pF
MHz
dB
dB
SYMBOL
I
COM(OFF)
I
COM(ON)
CONDITIONS
V
CC
= 3.6V, V
DP
= V
DM
= 0.3V to 3.3V,
V
TDP
= V
TDM
= 3.3V to 0.3V
V
CC
= 3.6V, V
DP
= V
DM
= 0.3V to 3.3V
MIN
-1
-1
TYP
1.5nA
90nA
MAX
+1
+1
UNITS
µA
µA
CDP HIGH-SPEED COMPARATORS
CDP LOW-SPEED COMPARATORS
www.maximintegrated.com
Maxim Integrated
│
3
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Electrical Characteristics (continued)
(V
CC
= 3.0V to 5.5V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 5.0V and T
A
= +25NC.) (Note 2)
PARAMETER
V
DP_REF
Voltage
V
LGC
Voltage
I
DP_SINK
Current
Input Logic High Voltage
Input Logic Low Voltage
Input Leakage Current
CB0/CB1 Debounce Time
INT,
SDA, CEN Output Low
Voltage
INT,
SDA, CEN Output Leakage
Current
CEN,
INT,
Output High Voltage
CEN,
INT,
Output Leakage Current
V
BUS
Toggle Time Accuracy
I
2
C Maximum Clock Frequency
Bus Free Time Between STOP
and START Conditions
START Condition Setup Time
Repeated START Condition
Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Valid to SCL Rise Time
Data Hold Time to SCL Fall
PROTECTION SPECIFICATIONS
ESD Protection
V
ESD
Human Body Model
DP and DM pins
All other pins
Q15
Q2
kV
SYMBOL
V
DP_REF
V
LGC
I
DP_SINK
V
IH
V
IL
I
IN
t
DEB_CB_
0V
P
V
IN
P
V
IL
or V
IH
P
V
IN
P
V
CC
,
V
CC
= 5.5V
-1
250
V
DP
= 0.15V to 3.6V
CONDITIONS
MIN
0.25
0.8
50
1.4
0.4
+1
TYP
MAX
0.4
2.0
150
UNITS
V
V
FA
V
V
FA
Fs
LOGIC INPUTS (CB0, CB1, SDA, SCL)
OPEN-DRAIN LOGIC OUTPUTS (SDA,
INT, CEN,
CEN)
V
OL
I
OH
V
OH
I
OL
t
VBT
f
SCL
t
BUF
t
SU:STA
t
SU:STA
t
HD:STA
t
SU:STO
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
70% of SCL to 70% of SDA
30% of SDA to 70% of SCL
70% of SCL to 30% of SDA
30% to 30%
70% to 70%
Write setup time
Write hold time
1.3
0.6
0.6
0.6
0.6
1.3
0.6
100
100
Output asserted, I
SINK
= 4mA
Output not asserted, V
CC
= V
OUT
= 5.5V
Output asserted, I
SOURCE
= 4mA
Output not asserted, V
CC
= 5.5V, V
CEN
= 0V
Q10
400
V
CC
- 0.4
1
0.4
1
V
FA
V
FA
%
kHz
Fs
Fs
Fs
Fs
Fs
Fs
Fs
ns
ns
I
2
C TIMING CHARACTERISTICS (SEE FIGURE 4)
Note 2:
All units are production tested at T
A
= +25NC. Specifications over temperature are guaranteed by design.
Note 3:
The MAX1464_ is operational from 3.0V to 5.5V. However, in order for the valid Apple resistor-divider network to function,
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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