MM74HCT00 — Quad 2 Input NAND Gate
February 2008
MM74HCT00
Quad 2 Input NAND Gate
Features
■
TTL, LS pin-out and threshold compatible
■
Fast switching: t
PLH
, t
PHL
=
14ns (typ.)
■
Low power: 10µW at DC
■
High fan out, 10 LS-TTL loads
General Description
The MM74HCT00 is a NAND gates fabricated using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power
and wide power supply range. This device is input and
output characteristic and pin-out compatible with stan-
dard 74LS logic families. All inputs are protected from
static discharge damage by internal diodes to V
CC
and
ground.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power
consumption in existing designs.
Ordering InformationOrdering Information
Package
Order Number Number
MM74HCT00M
MM74HCT00SJ
MM74HCT00MTC
MM74HCT00N
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
(1 of 4 gates)
Top View
©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
www.fairchildsemi.com
MM74HCT00 — Quad 2 Input NAND Gate
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
Parameter
Rating
–0.5 to +7.0V
–1.5 to V
CC
+1.5V
–0.5 to V
CC
+0.5V
±20mA
±25mA
±50mA
–65°C to +150°C
600mW
500mW
260°C
DC V
CC
or GND Current, per pin
Storage Temperature Range
Power Dissipation
Note 2
S.O. Package only
Lead Temperature (Soldering 10 seconds)
T
L
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Supply Voltage
DC Input or Output Voltage
Parameter
Min.
4.5
0
–40
Max.
5.5
V
CC
+85
500
Units
V
V
°C
ns
Operating Temperature Range
Input Rise or Fall Times
©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
www.fairchildsemi.com
2
MM74HCT00 — Quad 2 Input NAND Gate
DC Electrical Characteristics
V
CC
=
5V ± 10% (unless otherwise specified)
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C
to 85°C
2.0
0.8
V
CC
– 0.1
3.84
T
A
=
–55°C
to 125°C
Units
2.0
0.8
V
CC
– 0.1
3.7
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
Conditions
Typ.
2.0
0.8
Guaranteed Limits
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
=
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
=
4.0mA,
V
CC
=
4.5V
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
=
4.8mA,
V
CC
=
5.5V
V
CC
4.2
V
CC
– 0.1
3.98
5.2
4.98
4.84
4.7
V
OL
Maximum LOW Level
Voltage
V
IN
=
V
IH
,
|I
OUT
|
=
20 µA
V
IN
=
V
IH
,
|I
OUT
|
=
4.0mA,
V
CC
=
4.5V
V
IN
=
V
IH
,
|I
OUT
|
=
4.8mA,
V
CC
=
5.5V
0
0.2
0.1
0.26
0.1
0.33
0.1
0.4
V
0.2
0.26
0.33
0.4
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND,
V
IH
or V
IL
V
IN
=
V
CC
or GND,
I
OUT
=
0 µA
V
IN
=
2.4V or 0.5V
(3)
0.18
±0.05
1.0
0.3
±0.5
10
0.4
±1.0
40
0.5
µA
µA
mA
Note:
3. This is measured per input with all other inputs held at V
CC
or ground.
©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
www.fairchildsemi.com
3
MM74HCT00 — Quad 2 Input NAND Gate
AC Electrical Characteristics
V
CC
= 5.0V, t
r
= t
r
= 6ns, C
L
= 15pF, T
A
= 25°C (unless otherwise noted)
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay
Conditions
Typ.
14
Guaranteed
Limit
18
Units
ns
AC Electrical Characteristics
V
CC
= 5.0V ±10%, t
r
= t
f
= 6ns, C
L
= 50pF (unless otherwise noted)
T
A
=
25°C
Symbol
t
PLH
, t
PHL
t
THL
, t
TLH
C
PD
C
IN
T
A
=
–40°C
to 85°C
29
19
T
A
=
–55°C
to 125°C
Units
ns
ns
pF
35
22
Parameter
Maximum Propagation Delay
Maximum Output Rise and
Fall Time
Power Dissipation
Capacitance
Input Capacitance
Conditions
Typ.
18
8
23
15
Guaranteed Limits
(4)
30
5
10
10
10
pF
Note:
4. C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
=
C
PD
V
CC
f + I
CC
.
©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
www.fairchildsemi.com
4
MM74HCT00 — Quad 2 Input NAND Gate
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
1.70
C B A
PIN ONE
INDICATOR
1
1.27
(0.33)
0.51
0.35
0.25
M
7
1.27
LAND PATTERN RECOMMENDATION
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
0.25
0.19
R0.10
R0.10
8°
0°
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
www.fairchildsemi.com
5
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