74LVQ244
LOW VOLTAGE OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
=5.6 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.4V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 244
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
DESCRIPTION
The 74LVQ244 is a low voltage CMOS OCTAL
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
Figure 1: Pin Connection And Iec Logic Symbols
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
technology. It is ideal for low power and low noise
3.3V applications.
G control output governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
te
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P
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d
74LVQ244MTR
74LVQ244TTR
s)
t(
July 2004
Rev. 7
1/12
74LVQ244
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 4, 6, 8
9, 7, 5, 3
11, 13, 15,
17
18, 16, 14,
12
19
10
20
SYMBOL
1G
1A1 to 1A4
2Y1 to 2Y4
2A1 to 2A4
1Y1 to 1Y4
2G
GND
V
CC
NAME AND FUNCTION
Output Enable Input
Data Inputs
Data Outputs
Data Inputs
Data Outputs
Output Enable Input
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
G
L
L
H
X : Don’t Care
Z : High Impedance
OUTPUT
An
L
H
X
Yn
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
so
b
O
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Table 5: Recommended Operating Conditions
Parameter
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
Value
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
0 to 10
Unit
V
V
V
°C
ns/V
ro
P
te
le
du
(s
ct
-
)
so
b
O
te
le
ro
P
uc
d
L
H
Z
s)
t(
Unit
V
V
V
mA
mA
mA
mA
°C
°C
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Lead Temperature (10 sec)
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
2/12
74LVQ244
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
2.0
0.8
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
V
OL
Low Level Output
Voltage
I
O
=50
µA
3.0
I
O
=12 mA
I
O
=24 mA
I
I
Ioz
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
3.6
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
±
0.1
±
0.5
4
0.002
0
0.1
0.36
2.9
2.58
2.99
2.9
2.48
2.2
0.1
0.44
0.55
±
1
±
5
40
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
0.1
0.44
V
0.55
±
1
V
Max.
-55 to 125°C
Min.
2.0
0.8
Max.
V
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
I
CC
I
OLD
I
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
V
OLP
V
OLV
V
IHD
so
b
O
V
ILD
r
P
te
le
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
du
o
3.3
(s
ct
-
)
so
b
O
Min.
0.4
-0.8
2
et
l
P
e
36
-25
Value
od
r
uc
25
-25
s)
t(
±
10
40
µA
µA
µA
mA
mA
T
A
= 25°C
Typ.
Max.
0.8
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
-0.5
V
V
C
L
= 50 pF
0.8
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
3/12
74LVQ244
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
T
A
= 25°C
Min.
Typ.
6.6
5.6
8.3
6.8
7.5
6.0
0.5
0.5
Max.
11
9
13.5
10
12
9.0
1.0
1.0
Value
-40 to 85°C
Min.
Max.
12.5
10.5
15
11.5
13.5
10.5
1.0
1.0
-55 to 125°C
Min.
Max.
14
13
18
13
15
12
1.0
1.0
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
3.3
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
8
Value
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per circuit)
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
10
te
le
Max.
-40 to 85°C
Min.
Max.
ro
P
uc
d
Min.
s)
t(
Max.
-55 to 125°C
Unit
pF
pF
pF
4/12
74LVQ244
Figure 3: Test Circuit
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
SWITCH
Open
Figure 4: Waveform - Propagation Delays
(f=1MHz; 50% duty cycle)
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
te
le
ro
P
uc
d
2V
CC
Open
s)
t(
5/12
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