Document CD00003411
Revision
1.3
IN APPROVAL
4 / 93
STA310
6+2-CH. MULTISTANDARD AUDIO DECODER
PRELYMINARY DATA
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FEATURES
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DVD Audio
decoder:
Meridian Lossless Packing
(
MLP
), with
up to 6 channels,
Uncompressed LPCM with 1-8 channels,
Precision of up to 24 bits and sample rates
of between 44.1 kHz and 192 kHz.
Dolby Digital
(*)
decoder:
Decodes 5.1
Dolby Digital Surround.
Output up to 6 channels. downmix modes:
1, 2, 3 or 4 channels.
MPEG
-1 2- channel audio decoder, layers I and
II.
MPEG-2 6-channel audio decoder, layer II.
24 bits decoding precision.
MP3 (MPEG layer III) decoder.
Accepts MPEG-2 PES stream format for:
MPEG-2, MPEG-1, Dolby Digital and linear
PCM.
Karaoke System.
Prologic decoder.
Downmix for Dolby Prologic compatible.
A separate (2-ch) PCM output available for
simultaneous playing and recording.
Bitstream input interface: serial, parallel or
SPDIF.
SPDIF and IEC-61937 input interface.
SPDIF and IEC-61937 output interface.
PLL for internal PCM clock generation.
frequencies supported: 44.1KHz family (22.05,
88.2, 176.4) and 48KHz family (24, 48, 96, 192).
PCM: transparent, downsampling 192 to 96 Khz
and 96 to 48kHz.
PTS handling control on-chip.
No external DRAM required
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2
C or parallel control bus
Embedded
Development RAM
for
customizable software capability.
Configurable internal PLLs for system and
audio clocks, from an externally provided clock.
80-PIN TQFP package
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June 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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2.5V (for core) and 3V (for I/O) power supply.
3V Capable I/O Pads .
True-SPDIF input receiver supporting AES/
EBU, IEC958, S/PDIF.
No external chip required.
Differential or single ended inputs can be
decoded.
APPLICATIONS
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High-end audio equipment.
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DVD consumer players.
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Set top box.
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HDTV .
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Multimedia PC.
(*)
“Dolby “, “AC-3”
and
“ProLogic”
are
trademarks of
Dolby Laboratories.
DESCRIPTION
The STA310 is a fully integrated Audio Decoder ca-
pable of decoding all the above listed formats.
Encoded input data can be entered either by a serial
(I2S or SPDIF) or a parallel interface. A second input
data stream (I2S) is available for micro input.
The control interface can be either
I
2
C
or a parallel 8-
bit interface. No external DRAM is necessary for a to-
tal of 35ms surround delays.
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TQFP80
ORDERING NUMBER:
STA310
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1/90
Copyright STMicroelectronics
Company Internal
Unauthorized reproduction and communication strictly prohibited
Document CD00003411
Revision
1.3
IN APPROVAL
5 / 93
STA310
2
STA310 AUDIO DECODER PIN DESCRIPTION
Pin Number
CONTROL INTERFACES
48
47
IRQB
SELI2C
O
(1)
I
(2)
Interrupt Signal (level), active low
Selects the Control Interface (when high: serial interface; when
low: parallel interface)
Name
Type
Function
I
2
C Control Interface
43
46
53
SDAI2C
SCLKI2C
MAINI2CADR
I/O
(1)
I
I
(2)
I
2
C Serial Data
I
2
C Clock
Determines the slave address
Parallel Control Interface
78 - 79 - 80 - 1
2-3-6-7
12 - 13 - 14 - 15
16 - 18 - 19 - 20
21
22
35
D0 - D1 - D2 - D3
D4 - D5 - D6 - D7
A0 - A1 - A2 - A3
A4 - A5 - A6 - A7
DCSB
R/W
WAITB
I/O
I
I
I
O
(3)
Host Data
Host Address
Chip Select, active low
Read/Write Selection: read access when high, write access
when low
Data Acknowledge, active low
DATA INPUT INTERFACE
First Serial Data Interface (I
2
S)
37
41
40
42
SIN
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62
60
61
63
Second Serial Data Interface (I
2
S)
DSTRB2
SIN2
LRCLKIN2
REQ2
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LRCLKIN
REQ
DATA OUTPUT INTERFACES
69
DAC Interface
67
SCLK
O
Bit Clock for the DAC
PCMCLK
I/O
Oversampling Clock input for STA310 when generated externally
2/90
Copyright STMicroelectronics
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Clock Input Data, active low
Serial Input Data
Word Clock for the Input
Handshake for the Data Transfer, aconfigurable by the
SIN_SETUP register
Clock Input Data, active low
Serial Input Data
Word Clock for the Input
Handshake for the Data Transfer, active low
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