DATASHEET
HD-6402/883
CMOS Universal AsynchronousReceiver Transmitter (UART)
FN2953
Rev 1.00
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 8.0MHz Operating Frequency (HD-6402/883B)
• 2.0MHz Operating Frequency (HD-6402/883R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
Description
The HD-6402/883 is a CMOS UART for interfacing comput-
ers or microprocessors to an asynchronous serial data chan-
nel. The receiver converts serial start, data, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start, parity and stop bits. The data
word length can be 5, 6, 7 or 8 bits. Parity may be odd or
even. Parity checking and generation can be inhibited. The
stop bits may be one or two or one and one-half when trans-
mitting 5-bit code.
The HD-6402/883 can be used in a wide range of applica-
tions including modems, printers, peripherals and remote
data acquisition systems. Utilizing the Intersil advanced
scaled SAJI IV CMOS process permits operation clock fre-
quencies up to 8.0MHz (500K Baud). Power requirements,
by comparison, are reduced from 300mW to 10mW. Status
logic increases flexibility and simplifies the user interface.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
-55
o
C to +125
o
C
2MHz = 125K BAUD
HD1-6402R/883
8MHz = 500K BAUD
HD1-6402B/883
PKG. NO.
F40.6
Pinout
HD-6402/883 (CERDIP)
TOP VIEW
VCC
NC
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 TRC
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
FN2953 Rev 1.00
March 1997
Page 1 of 6
HD-6402/883
Control Definition
CONTROL WORD
CLS 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CLS 1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
PI
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
EPE
0
0
1
1
X
X
0
0
1
1
X
x
0
0
1
1
X
x
0
0
1
1
X
x
SBS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CHARACTER FORMAT
DATA BITS
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
PARITY BIT
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
STOP BITS
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
FN2953 Rev 1.00
March 1997
Page 2 of 6
HD-6402/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.5V to V
CC
+0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Typical Derating Factor. . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance
JA
JC
CERDIP Package . . . . . . . . . . . . . . . . 50
o
C/W
12
o
C/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
TABLE 1. HD-6402/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
MIN
2.3
-
-1.0
3.0
VCC
-0.4
-
-1.0
-
MAX
-
0.8
1.0
-
-
0.4
1.0
100
UNITS
V
V
A
V
V
V
A
A
D.C. PARAMETER
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Input Leakage Current
Logical ‘‘1’’ Output Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Output Leakage Current
Standby Supply Current
SYMBOL
VIH
VIL
IID
VOH
VOH
VOL
IO
ICCSB
CONDITIONS
VCC = 5.5V
VCC = 4.5V
VIN = GND or VCC,
VCC = 5.5V
IOH = -2.5mA,
VCC = 4.5V (Note 1)
IOH = -100A
VCC = 4.5V (Note 1)
IOL = +2.5mA,
VCC = 4.5V (Note 1)
VO = GND or VCC,
VCC = 5.5V
VIN = GND or VCC;
VCC = 5.5V,
Output Open
TABLE 2. HD-6402/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
HD-6402/883R
TEMPERATURE
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
MIN
-
150
150
50
60
-
MAX
2.0
-
-
-
-
160
LIMITS
HD-6402/883B
MIN
-
75
150
20
20
-
MAX
8.0
-
-
-
-
35
UNITS
MHz
ns
ns
ns
ns
ns
A.C.
PARAMETER
Clock Frequency
Pulse Widths,
CRL, DRR, TBRL
Pulse Width MR
Input Data Setup
Time
Input Data Hold
Time
Output Enable
Time
NOTE:
SYMBOL
(1) fCLOCK
(2) tPW
(3) tMR
(4) tSET
(5) tHOLD
(6) tEN
(NOTE 1)
CONDITIONS
VCC = 4.5V
CL = 50pF
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1. Interchanging of force and sense conditions is permitted.
2. Tested with input levels of VIH = 2.76V and VIL = 0.4V. Rise and fall times are driven at 1ns/V.
FN2953 Rev 1.00
March 1997
Page 3 of 6
HD-6402/883
TABLE 3. HD-6402/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
A.C. PARAMETER
Input Capacitance
Output Capacitance
Operating Supply Current
SYMBOL
CIN
CO
ICCOP
CONDITIONS
f = 1Mhz
All Measurements are
Referenced to Device GND
VCC = 5.5V,
Clock Freq. = 2MHz,
VIN = VCC or GND,
Outputs Open
NOTES
1
1
1
TEMPERATURE
T
A
= +25
o
C
T
A
= +25
o
C
-55
o
C
T
A
+125
o
C
MIN
-
-
-
MAX
25.0
25.0
2.0
UNITS
pF
pF
mA
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Group C and D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
FN2953 Rev 1.00
March 1997
Page 4 of 6
HD-6402/883
Burn-In Circuits
HD-6402/883 CERDIP
DETAIL
A
VCC
VCC
R1
C
A
R1
GND
GND
R1
1
2
3
4
40
39
38
37
36
35
34
33
32
DIP
HD-6402/883
31
30
29
28
27
26
25
24
23
22
21
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
F0
VCC
VCC
VCC
VCC
GND
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
A
A
5
6
7
8
9
10
11
12
13
14
R1
15
16
R1
17
18
DETAIL
B
VCC
A
A
C
NOTE: ONE PER BOARD
A
A
A
A
A
A
A
GND
1
2
3
4
5
6
7
4011
QUAD
NAND
GATE
14
13
12
11
10
9
8
B
C (NOTE 5)
F0
F0
VCC
A
B
R1
(NOTE 5)
A
19
20
A
GND
NOTES:
1. VCC = 5.5V
0.5V
2. F0 = 100kHz
10%
3. R1 = 47k, 1/4W
10%
4. C = 0.01F minimum
5. One socket per board should not be loaded, but rather have pin 24 go the “C” of the 4011.
FN2953 Rev 1.00
March 1997
Page 5 of 6
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