1-to-2, LVCMOS/LVTTL-to-Differential
HSTL Translator
G
ENERAL
D
ESCRIPTION
The 85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL
translator. The 85222-02 has one single ended clock input. The
single-ended clock input accepts LVCMOS or LVTTL input levels
and translates them to HSTL levels. The small outline 8-pin SOIC
package makes this device ideal for applications where space, high
performance and low power are important.
85222-02
DATASHEET
F
EATURES
•
Two differential HSTL outputs
•
One LVCMOS/LVTTL clock input
•
CLK input can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 350MHz
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.25ns (maximum)
•
V
OH
: 1.4V (maximum)
•
Output crossover voltage: 0.68V - 0.9V
•
Full 3.3V operating supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
Q0
CLK
Pulldown
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK
nc
GND
85222-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
85222-02 REVISION B 6/15/15
1
©2015 Integrated Device Technology, Inc.
85222-02 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
nc
CLK
V
DD
Type
Output
Output
Power
Unused
Input
Power
Description
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
No connect.
Pulldown LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
2
REVISION B 6/15/15
85222-02 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
1.0
0
0.68
0.6
1.0
Typical
Maximum
1.4
0.4
0.9
1.4
Units
V
V
V
V
NOTE 1: All outputs must be terminated with 50Ω to ground.
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
f
≤
250MHz
f > 250MHz
250
45
40
0.85
1.05
Test Conditions
Minimum
Typical
Maximum
350
1.25
25
250
500
55
60
Units
MHz
ns
ps
ps
ps
%
%
All outputs must be terminated with 50W to ground.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
REVISION B 6/15/15
3
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
85222-02 DATA SHEET
P
ARAMETER
M
EASUREMENT
I
NFORMATION
NOTE: All outputs must be terminated with 50Ω to ground.
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
4
REVISION B 6/15/15
85222-02 DATA SHEET
A
PPLICATION
I
NFORMATION
R
ECOMMENDATIONS FOR
U
NUSED
O
UTPUT
P
INS
O
UTPUTS
:
HSTL O
UTPUT
All outputs must be terminated with 50Ω to ground.
S
CHEMATIC
E
XAMPLE
Figure 2 shows a schematic example of 85222-02. In the example,
the input is driven by a 7 ohm LVCMOS driver with a series
termination. The decoupling capacitor should be physically located
near the power pin. For 85222-02, the unused output need to be
terminated.
VDD=3.3V
Q2
Ro ~ 7 Ohm
R6
Driv er_LVCMOS
43
Zo = 50 Ohm
5
6
7
8
Zo = 50 Ohm
U1
GND
nc
CLK
VDD
nQ1
Q1
nQ0
Q0
ICS85222-02
C1
0.1u
Zo = 50 Ohm
-
Zo = 50 Ohm
+
R3
50
R4 HSTL Input
50
4
3
2
1
Zo = 50 Ohm
+
R1
50
R2
50 HSTL Input
-
VDD=3.3V
F
IGURE
2. 85222-02 HSTL B
UFFER
S
CHEMATIC
E
XAMPLE
REVISION B 6/15/15
5
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
ARM技术
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