ST16C580
UART WITH 16-BYTE FIFO’s AND
INFRARED (IrDA) ENCODER/DECODER
August 2005
GENERAL DESCRIPTION
The ST16C580
1
is a universal asynchronous receiver and transmitter (UART) and is pin compatible with the ST16C550
UART. The 580 is an enhanced UART with 16 byte FIFO’s, automatic hardware/software flow control, and data rates
up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status. Modem
interface control is included and can be optionally configured to operate with the Infrared (IrDA) encoder/decoder. The
system interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard
diagnostics. The 580 is available in the 48 pin TQFP package. It is fabricated in an advanced CMOS process to achieve
low drain power and high speed requirements.
48 Pin TQFP Package
-DSR
-CTS
38
VCC
N.C.
FEATURES
•
Pin to pin and functionally compatible to the Industry
Standard 16550
•
2.97 to 5.5 volt operation
•
1.5 Mbps transmit/receive operation (24MHz)
•
16 byte transmit FIFO
•
16 byte receive FIFO with error flags
•
Automatic hardware/software flow control
•
Programmable Xon/Xoff characters
•
Independent transmit and receive control
•
Software selectable Baud Rate Generator pre-
scaleable clock rates of 1X or 4X
•
Four selectable transmit/receive FIFO interrupt trig-
ger levels
•
Standard modem interface or Infrared IrDA encode/
decoder interface
•
Sleep mode ( 200µA stand-by )
•
Low operating current ( 1.2mA typ.)
N.C.
D5
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
-CS2
-BAUDOUT
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
37
N.C.
-CD
-RI
D4
D3
D2
D1
D0
36
35
34
33
32
N.C.
RESET
-OP1
-DTR
-RTS
-OP2
INT
-RXRDY
A0
A1
A2
N.C.
XR16C580CQ48
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
-TXRDY
N.C.
GND
N.C.
XTAL1
ORDERING INFORMATION
Part number
Package
Operating temp
Device Status
ST16C580CQ48
ST16C580IQ48
48-Lead TQFP
48-Lead TQFP
0° C to + 70° C
-40° C to + 85° C
Active
Active
*Note 1 Covered by U.S. Patent #5,649,122.
Rev. 1.22
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
XTAL2
-DDIS
-IOW
IOW
-IOR
IOR
-AS
24
ST16C580
Figure 2, BLOCK DIAGRAM
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Data bus
&
Control Logic
Transmit
FIFO
Registers
Transmit
Shift
Register
TX
Flow
Control
Logic
Receive
FIFO
Registers
Ir
Encoder
Inter Connect Bus Lines
&
Control signals
A0-A2
-AS
CS0,CS1
-CS2
-DDIS
Register
Select
Logic
Receive
Shift
Register
RX
INT
-RXRDY
-TXRDY
Interrupt
Control
Logic
Flow
Control
Logic
Ir
Decoder
-DTR,-RTS
-OP1,-OP2
Clock
&
Baud Rate
Generator
Modem
Control
Logic
-CTS
-RI
-CD
-DSR
XTAL1
RCLK
XTAL2
-BAUDOUT
Rev. 1.22
2
ST16C580
SYMBOL DESCRIPTION
Symbol
A0
A1
A2
IOR
Pin
48
28
27
26
20
Signal
type
I
I
I
I
Pin Description
Address-0 Select Bit - Internal registers address selection.
Address-1 Select Bit Internal registers address selection.
Address-2 Select Bit Internal registers address selection.
Read strobe. Its function is the same as -IOR (see -IOR),
except it is active high. Either an active -IOR or IOR is
required to transfer data from 580 to CPU during a read
operation.
Chip Select-0. A logical 1 on this pin provides the chip select
0 function.
Chip Select-1. A logical 1 on this pin provides the chip select
1 function.
Chip Select -2. A logical 0 on this pin provides the chip select
2 function.
Write strobe. A logic 1 transition creates a write strobe. Its
function is the same as -IOW (see -IOW), but it acts as an
active high input signal. Either -IOW or IOW is required to
transfer data from the CPU to 580 during a write operation.
Address Strobe. A logic 1 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable for
the duration of a read or write operation, i.e., a microprocessor
that needs to de-multiplex the address and data bits. If not
required, the -AS input can be permanently tied to a logic 0
(it is edge triggered).
CS0
9
I
CS1
10
I
-CS2
11
I
IOW
17
I
-AS
24
I
D0-D7
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and Power Ground.
GND
18
Pwr
Rev. 1.22
3
ST16C580
SYMBOL DESCRIPTION
Symbol
-IOR
Pin
48
19
Signal
type
I
Pin Description
Read strobe (active low strobe). A logic 0 on this pin transfers
the contents of the 580 data bus to the CPU.
Write strobe (active low strobe) - A logic 0 on this pin transfers
the contents of the CPU data bus to the addressed internal
register.
Interrupt Request.
Receive Ready. A logic 0 indicates receive data ready status,
i.e. the RHR is full or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 0 when the
FIFO/RHR is full or when there are more characters available
in either the FIFO or RHR.
Transmit Ready. Buffer ready status is indicated by a logic
0, i.e., at least one location is empty and available in the
FIFO or THR. This pin goes to a logic 1 when there are no
more empty locations in the FIFO or THR.
Baud Rate Generator Output. This pin provides the 16X clock
of the selected data rate from the baud rate generator. The
RCLK pin must be connected externally to -BAUDOUT when
the receiver is operating at the same data rate.
Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the 580. This signal can be used
to disable external transceivers or other logic functions.
Output-1 (User Defined) - See bit-2 of modem control register
(MCR bit-2).
Output-2 (User Defined). This pin provides the user a general
purpose output. See bit-3 modem control register (MCR bit-
3).
Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rate generator.
-IOW
16
I
INT
-RXRDY
30
29
O
O
-TXRDY
23
O
-BAUDOUT
12
O
-DDIS
22
O
-OP1
34
O
-OP2
31
O
RCLK
5
I
Rev. 1.22
4
ST16C580
SYMBOL DESCRIPTION
Symbol
RESET
Pin
48
35
Signal
type
I
Pin Description
Reset. (active high) - A logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output
and the receiver input will be disabled during reset time. (See
ST16C580 External Reset Conditions for initialization de-
tails.)
Power Supply Input.
Crystal or External Clock Input - Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. An external 1 M resistor is required between the
XTAL1 and XTAL2 pins (see figure 9). Alternatively, an
external clock can be connected to this pin to provide
custom data rates (Programming Baud Rate Generator
section).
Output of the Crystal Oscillator or Buffered Clock - (See also
XTAL1). Crystal oscillator output or buffered clock output.
Carrier Detect (active low) - A logic 0 on this pin indicates that
a carrier has been detected by the modem.
Clear to Send (active low) - A logic 0 on the -CTS pin indicates
the modem or data set is ready to accept transmit data from
the 580. Status can be tested by reading MSR bit-4. This pin
only affects the transmit and receive operations when Auto
CTS function is enabled via the Enhanced Feature Register
(EFR) bit-7, for hardware flow control operation.
Data Set Ready (active low) - A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data
exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
Data Terminal Ready (active low) - A logic 0 on this pin
indicates that the 580 is powered-on and ready. This pin can
be controlled via the modem control register. Writing a logic
1 to MCR bit-0 will set the -DTR output to logic 0, enabling
the modem. This pin will be a logic 1 after writing a logic 0
to MCR bit-0, or after a reset. This pin has no effect on the
UART’s transmit or receive operation.
VCC
XTAL1
42
14
Pwr
I
XTAL2
15
O
-CD
40
I
-CTS
38
I
-DSR
39
I
-DTR
33
O
Rev. 1.22
5
PCB设计
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