CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions is using a max positive pulse of 6.5V on the WP pin.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
TEST CONDITIONS
R
TOTAL
= (V
RH
- V
RL
)/I
DCP
W option
U option
MIN
(Note 18)
TYP
(Note 4)
10
50
-20
V
CC
= 3.3V @ +25°C
Wiper current = V
CC
/R
TOTAL
Wiper at the middle scale, 1kHz 1V
RMS
input to RH pin
70
-110
10/10/25
Voltage at pin from GND to V
CC
0.1
1
+20
200
MAX
(Note 18)
UNIT
kΩ
kΩ
%
Ω
dBV
pF
µA
R
H
to R
L
Resistance
R
H
to R
L
Resistance Tolerance
R
W
R
Wnoise
(Note 16)
C
H
/C
L
/C
W
(Note 16)
I
LkgDCP
Wiper Resistance
Noise Level
Potentiometer Capacitance
Leakage on DCP Pins
VOLTAGE DIVIDER MODE
(0V @ RL; V
CC
@ RH; measured at RW, unloaded)
INL (Note 9)
Integral Non-Linearity
DCP register set between 1 hex and FFhex.
Monotonic over all tap positions.
W and U options
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions
W option
U option
FSerror (Note 7) Full-Scale Error
W option
U option
TC
V
(Note 10, 16)
f
CUTOFF
(Note 16)
Ratiometric Temperature
Coefficient
3dB Cut-Off Frequency
DCP Register set to 80 hex
Wiper at the middle scale
W option
U option
W option
U option
-1
1
LSB
(Note 5)
LSB
(Note 5)
LSB
(Note 5)
LSB
(Note 5)
ppm/°C
kHz
kHz
DNL (Note 8)
Differential Non-Linearity
-0.75
-0.5
0
0
-5
-2
1
0.5
-1
-0.5
±4
1250
250
0.75
0.5
5
2
0
0
ZSerror (Note 6) Zero-Scale Error
3
FN6759.1
October 6, 2008
ISL95811
Analog Specifications
SYMBOL
Over recommended operating conditions unless otherwise stated.
(Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 4)
MAX
(Note 18)
UNIT
RESISTOR MODE
(Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL (Note 14)
Integral Non-Linearity
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions.
W option
U option
W option
U option
-3
-1
-0.75
-0.5
0
0
1
0.5
±45
3
1
0.75
0.5
5
2
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
ppm/°C
RDNL (Note 13) Differential Non-Linearity
DCP register set between 1 hex
and FF hex. Monotonic over all
tap positions
R
offset
(Note 12) Offset
W option
U option
TC
R
(Note 15, 16)
Resistance Temperature
Coefficient
DCP register set between 20 hex and FF
hex
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
CC2
I
SB
PARAMETER
V
CC
Supply Current
(Volatile Write/Read)
V
CC
Supply Current
(Non-volatile Write)
V
CC
Current (Standby)
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Non-volatile Write State only)
V
CC
= +5.5V, I
2
C Interface in Standby State
V
CC
= +3.6V, I
2
C Interface in Standby State
I
LkgDig
t
DCP
Vpor
V
CC
Ramp
t
D
Leakage Current, at Pins SDA, SCL, Voltage at pin from GND to V
CC
and WP Pins
DCP Wiper Response Time
Power-On Recall Voltage
V
CC
Ramp Rate
Power-Up Delay
V
CC
above V
POR
, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
SCL falling edge of last bit of DCP Data
Byte to wiper change
Minimum V
CC
at which memory recall occurs
1.8
0.2
3
-1
MIN
TYP
MAX
(Note 18) (Note 4) (Note 18) UNITS
100
2
10
5
1
1
2.6
µA
mA
µA
µA
µA
µs
V
V/ms
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
SERIAL INTERFACE SPECIFICATIONS
V
IL
V
IH
WP, SDA, and SCL Input Buffer LOW
Voltage
WP, SDA, and SCL Input Buffer
HIGH Voltage
-0.3
0.7*V
CC
0.05*V
CC
0
0.4
10
0.3*V
CC
V
CC
+
0.3
V
V
V
V
pF
Temperature
≤ +55°C
1,000,000
50
Cycles
Years
Hysteresis (Note 16) SDA and SCL Input Buffer Hysteresis
V
OL
Cpin (Note 16)
SDA Output Buffer LOW Voltage,
Sinking 4mA
WP, SDA, and SCL Pin Capacitance
4
FN6759.1
October 6, 2008
ISL95811
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
f
SCL
t
IN
t
AA
t
BUF
PARAMETER
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
1300
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 4) (Note 18) UNITS
400
50
900
kHz
ns
ns
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
t
SU:STO
t
HD:STO
t
HD:STO:NV
t
DH
Input Data Hold Time
STOP Condition Setup Time
0
600
600
2
0
ns
ns
ns
µs
ns
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both
or Volatile Only Write
crossing 70% of V
CC
.
STOP Condition Hold Time for Non- From SDA rising edge to SCL falling edge. Both
Volatile Write
crossing 70% of V
CC
.
Output Data Hold Time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
From 70% to 30% of V
CC
Total on-chip and off-chip
t
R
(Note 16)
t
F
(Note 16)
Cb (Note 16)
Rpu (Note 16)
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
20 +
0.1 * Cb
20 +
0.1 * Cb
10
1
250
250
400
ns
ns
pF
kΩ
SDA and SCL Bus Pull-Up Resistor Maximum is determined by t
R
and t
F
.
Off-Chip
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
Non-Volatile Write Cycle Time
WP Setup Time
WP Hold Time
Before START condition
After STOP condition
t
WC
(Note 17)
t
SU:WP
t
HD:WP
NOTES:
12
600
600
20
ms
ns
ns
4. Typical values are for T
A
= +25°C and 3.3V supply voltage.
5. LSB: [V(RW)
255
– V(RW)
0
]
/
255. V(RW)
255
and V(RW)
0
are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW)
0
/
LSB.
7. FS error = [V(RW)
255
– V
CC
]
/
LSB.
8. DNL = [V(RW)
i
– V(RW)
i-1
]
/
LSB-1, for i = 1 to 255. i is the DCP register setting.
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