CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
BIAS
IC Supply Current
VDD Power On
VDD Power On Reset
PGOOD
Pull-Down Current
Pull-Up Resistance
Output Low
Delay from VMON Rising
Delay from EN Rising
Delay from EN Falling
ENABLE
Rising Threshold
Threshold Hysteresis
Pull-up Current
VMON Input
Falling Threshold
Falling Threshold Temp Coeff.
Hysteresis
Range
Glitch Filter Duration
NOTE:
Nominal VDD = 3.3V, T
A
= T
J
= -40°C - 85°C, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
I
VDD
VDD_L2H
VDD_POR
VMON > VMON
_L2H
VDD low to high
VDD high to low
165
2.6
2.4
1000
µA
V
V
PG
pd
PG
pu
VPGOOD = 0.5V
2
20
mA
k
0.1
V
µs
µs
µs
V
PGl
t
PG
delVMON
t
PG
delENR
t
PG
delENF
V
DD
= 1V
Last valid input = Vth to PG release
EN high to PG release
EN low to PG pulling low
0.05
2
0.05
0.015
V
EN
V
EN_HYS
I
ENpu
ENABLE Low to High Threshold
0.4VDD
0.5VDD
0.065
0.6VDD
V
V
µA
VEN = 0.5V
10
3.3VMON
_H2L
3.3VMON
_TC
VVMON
_HYS
VMON
_RNG
TFIL
T
J
= +25°C
0.623
0.633
100
0.643
V
uV/°C
-
-
VMON glitch to PGOOD low Filter
-
10
8
30
-
-
-
mV
mV
µs
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN9114 Rev 3.00
Jan 25, 2011
Page 3 of 7
ISL6536
ISL6536 Description and Operation
The ISL6536 is a four channel supervisory IC designed to
monitor multiple voltages greater than 0.7V. This IC is
suitable for both microprocessors or industrial system
applications.
Upon VDD bias power up the PGOOD output is held low
with VDD as low as 0V. Once biased to 2.6V and enabled
the IC continuously monitors from one to four voltages
independently through external resistor dividers comparing
each VMON pin voltage to an internal 0.63V reference.
Once all VMON input voltages rise above 0.63V the PGOOD
(power good) output signal is released and is pulled high via
an external pull resistor to indicate that the power conditions
have been met. The PGOOD output is an open-drain to
allow ORing of the signals and interfacing to a wide range of
logic levels.
Once any VMON input falls below 0.63V the PGOOD output
is pulled low, the VMON inputs are designed to reject fast
transients (30µs).
If less than four voltages are being monitored, connect the
unused VMON pins to VDD.
The PGOOD pin has an internal 20k
pull-up to VDD
making an external pull-up resistor unnecessary.
Figure 1 illustrates the operational timing diagram.
FPGA/CPLD
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