CBT3126
Quad FET bus switch
Rev. 04 — 12 October 2009
Product data sheet
1. General description
The CBT3126 is a quad FET bus switch with independent line switches. Each switch is
disabled when the associated Output Enable (OE) input is LOW.
The CBT3126 is characterized for operation from
−40 °C
to +85
°C.
2. Features
I
I
I
I
I
I
I
Standard ’126-type pinout
Multiple package options
5
Ω
switch connection between two ports
TTL-compatible input levels
Minimal propagation delay through the switch
Latch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Specified from
−40 °C
to +85
°C
3. Ordering information
Table 1.
Ordering information
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Package
Name
CBT3126D
CBT3126DB
CBT3126PW
CBT3126DS
SO14
SSOP14
TSSOP14
SSOP16
[1]
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT519-1
Type number
[1]
Also known as QSOP16.
NXP Semiconductors
CBT3126
Quad FET bus switch
4. Functional diagram
2
1
5
4
9
10
12
13
001aaj024
1OE
1A
2OE
2A
3OE
3A
4OE
4A
4B
3B
2B
1B
1A
1OE
2A
2OE
3A
3OE
4A
4OE
001aaj023
3
1B
6
2B
8
3B
11 4B
Pin numbers are for the 14 pin packages.
Fig 1.
Logic symbol
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
CBT3126
1OE
1A
1B
2OE
2A
2B
GND
1
2
3
4
5
6
7
001aaj111
14 V
CC
13 4OE
12 4A
11 4B
10 3OE
9
8
3A
3B
1OE 1
1A 2
1B 3
2OE 4
2A 5
2B 6
GND 7
001aaj025
CBT3126
CBT3126
n.c.
14 V
CC
13 4OE
12 4A
11 4B
10 3OE
9 3A
8 3B
1OE
1A
1B
2OE
2A
2B
GND
1
2
3
4
5
6
7
8
001aaj026
16 V
CC
15 4OE
14 4A
13 4B
12 3OE
11 3A
10 3B
9
n.c.
Fig 3.
Pin configuration
SOT108-1 (SO14)
Fig 4.
Pin configuration
SOT337-1 (SSOP14) and
SOT402-1 (TSSOP14)
Fig 5.
Pin configuration
SOT519-1 (SSOP16)
5.2 Pin description
Table 2.
Symbol
1OE to 4OE
1A to 4A,
1B to 4B
CBT3126_4
Pin description
Pin
SOT108-1 SOT337-1 and SOT402-1
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
SOT519-1
2, 5, 12, 15
3, 6, 11, 14
4, 7, 10, 13
output enable input
A input/output
B output/input
© NXP B.V. 2009. All rights reserved.
Description
Product data sheet
Rev. 04 — 12 October 2009
2 of 13
NXP Semiconductors
CBT3126
Quad FET bus switch
Table 2.
Symbol
GND
V
CC
n.c.
Pin description
…continued
Pin
SOT108-1 SOT337-1 and SOT402-1
7
14
-
SOT519-1
8
16
1, 9
ground (0 V)
positive supply voltage
not connected
Description
6. Functional description
Table 3.
Function selection
H = HIGH voltage level; L = LOW voltage level.
Inputs
nOE
L
H
nA to nB disconnected
nA to nB connected
Switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
CC
V
I
I
SW
I
IK
T
stg
P
tot
supply voltage
input voltage
switch current
input clamping current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
SO14 package
SSOP14 and SSOP16 package
TSSOP14 package
[1]
[2]
[3]
[4]
[2]
[3]
[4]
[4]
[1]
Conditions
Min
−0.5
−0.5
-
−50
−65
-
-
-
Max
+7.0
+7.0
128
-
+150
500
500
500
Unit
V
V
mA
mA
°C
mW
mW
mW
continuous current through each switch
V
I
< 0 V
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The package thermal impedance is calculated from JESD51-7.
For SO14 package; P
tot
derates linearly with 8 mW/K above 70
°C.
For SSOP14, SSOP16 and TSSOP14 packages; P
tot
derates linearly with 5.5 mW/K above 70
°C.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
Symbol
V
CC
V
IH
V
IL
T
amb
CBT3126_4
Parameter
supply voltage
HIGH-level input voltage
LOW-level input voltage
ambient temperature
Conditions
Min
4.5
2.0
-
Max
5.5
-
0.8
+85
Unit
V
V
V
°C
operating in free-air
−40
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 12 October 2009
3 of 13
NXP Semiconductors
CBT3126
Quad FET bus switch
9. Static characteristics
Table 6.
Static characteristics
T
amb
=
−
40
°
C to +85
°
C.
Symbol
V
IK
V
pass
I
I
I
CC
∆I
CC
Parameter
input clamping voltage
pass voltage
input leakage current
supply current
additional supply current
Conditions
V
CC
= 4.5 V; I
I
=
−18
mA
V
I
= V
CC
= 5.0 V; I
SW
=
−100 µA
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
SW
= 0 mA;
V
I
= V
CC
or GND
control pins; per input;
V
CC
= 5.5 V; one input at 3.4 V,
other inputs at V
CC
or GND
control pins; V
I
= 3 V or 0 V
V
O
= 3 V or 0 V; nOE = V
CC
V
CC
= 4.0 V
V
I
= 2.4 V; I
I
= 15 mA
V
CC
= 4.5 V
V
I
= 0 V; I
I
= 64 mA
V
I
= 0 V; I
I
= 30 mA
V
I
= 2.4 V; I
I
= 15 mA
[1]
[2]
[3]
All typical values are measured at V
CC
= 5 V; T
amb
= 25
°C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (A or B) terminals.
[3]
[2]
Min
-
-
-
-
-
Typ
[1]
-
3.8
-
-
-
Max
−1.2
-
±1
3
2.5
Unit
V
V
µA
µA
mA
C
I
C
io(off)
R
ON
input capacitance
off-state input/output capacitance
ON resistance
-
-
-
-
-
-
1.7
3.4
16
5
5
10
-
-
22
7
7
15
pF
pF
Ω
Ω
Ω
Ω
10. Dynamic characteristics
Table 7.
Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 4.5 V to 5.5 V; for test circuit see
Figure 8.
Symbol
t
pd
t
en
t
dis
[1]
[2]
Parameter
propagation delay
enable time
disable time
Conditions
nA to nB or nB to nA; see
Figure 6
nOE to nA or nB; see
Figure 7
nOE to nA or nB; see
Figure 7
[1][2]
[2]
[2]
Min
-
1.6
1.0
Max
0.25
4.5
5.4
Unit
ns
ns
ns
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
t
PLH
and t
PHL
are the same as t
pd
;
t
PZL
and t
PZH
are the same as t
en
;
t
PLZ
and t
PHZ
are the same as t
dis
.
CBT3126_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 12 October 2009
4 of 13
NXP Semiconductors
CBT3126
Quad FET bus switch
11. AC waveforms
V
I
input
0V
t
PHL
V
OH
output
V
OL
V
M
V
M
001aai367
V
M
V
M
t
PLH
Measurement points are given in
Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6.
The input (nA, nB) to output (nB, nA) propagation delay times
V
I
nOE input
GND
t
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
OL
t
PHZ
V
OH
output
HIGH-to-OFF
OFF-to-HIGH
GND
switch
enabled
switch
disabled
switch
enabled
001aaj027
V
M
t
PZL
V
M
V
X
t
PZH
V
Y
V
M
Measurement points are given in
Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7.
Table 8.
Input
V
M
1.5 V
Enable and disable times
Measurement points
Output
V
M
1.5 V
V
X
V
OL
+ 0.3 V
V
Y
V
OH
−
0.3 V
CBT3126_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 12 October 2009
5 of 13
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