®
ISL6207
Data Sheet
December 2, 2005
FN9075.8
High Voltage Synchronous Rectified Buck
MOSFET Driver
The ISL6207 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology in mobile
computing applications. This driver, combined with an Intersil
Multi-Phase Buck PWM controller, such as ISL6223, ISL6215,
and ISL6216, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6207 features 4A typical sink current for the lower gate
driver. The 4A typical sink current is capable of holding the
lower MOSFET gate during the Phase node rising edge to
prevent the shoot-through power loss caused by the high dv/dt
of the Phase node. The operation voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
The ISL6207 also features a three-state PWM input that,
working together with most of Intersil multiphase PWM
controllers, will prevent a negative transient on the output
voltage when the output is being shut down. This feature
eliminates the Schottky diode, that is usually seen in a
microprocessor power system for protecting the
microprocessor, from reversed-output-voltage damage.
The ISL6207 has the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable
of driving a 3000pF load with a 15ns propagation delay and
less than a 10ns transition time. This product implements
bootstrapping on the upper gate with an internal bootstrap
Schottky diode, reducing implementation cost, complexity,
and allowing the use of higher performance, cost effective
N-Channel MOSFETs. Adaptive shoot-through protection is
integrated to prevent both MOSFETs from conducting
simultaneously.
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• 30V Operation Voltage
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise Time
- Short Propagation Delays
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel and AMD
®
Mobile
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converters
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
Pinouts
ISL6207 (SOIC-8)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 EN
6 VCC
5 LGATE
BOOT 1
PWM 2
3
GND
4
LGATE
6 EN
6
5 VCC
ISL6207 (QFN)
TOP VIEW
PHASE
7
UGATE
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Intel® is a registered trademark of Intel Corporation.
AMD® is a registered trademark of Advanced Micro Devices, Inc.
ISL6207
Ordering Information
PART
NUMBER
ISL6207CB
ISL6207CBZ
(Note)
PART
MARKING
ISL6207CB
ISL6207CBZ
TEMP.
RANGE (°C)
-10 to 85
-10 to 85
-10 to 85
-10 to 85
-10 to 85
-10 to 85
-10 to 100
-10 to 100
PACKAGE
8 Lead SOIC
8 Lead SOIC
(Pb-free)
8 Lead SOIC
(Pb-free)
PKG.
DWG. #
M8.15
M8.15
M8.15
ISL6207CBZA ISL6207CBZ
(Note)
ISL6207CR
ISL6207CRZ
(Note)
207C
07CZ
8 Lead 3x3 QFN L8.3x3
8 Lead 3x3 QFN L8.3x3
(Pb-free)
8 Lead 3x3 QFN L8.3x3
(Pb-free)
8 Ld SOIC (Pb-
free)
8 Ld 3x3 QFN
(Pb-free)
M8.15
L8.3x3
ISL6207CRZA 07CZ
(Note)
ISL6207HBZ
(Note)
ISL6207HRZ
(Note)
ISL6207HBZ
07HZ
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL6207 Block Diagram
VCC
EN
VCC
10K
PWM
10K
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
VCC
BOOT
UGATE
PHASE
LGATE
GND
THERMAL PAD (FOR QFN PACKAGE ONLY)
2
FN9075.8
December 2, 2005
ISL6207
Typical Application - Two Phase Converter Using ISL6207 Gate Drivers
V
BAT
+5V
+5V
+5V
VCC
FB
VCC
VSEN
PGOOD
PWM1
PWM2
COMP
EN
PWM
DRIVE
ISL6207
BOOT
UGATE
PHASE
LGATE
+V
CORE
MAIN
CONTROL
VID
ISEN1
ISEN2
+5V
V
BAT
VCC
FS
DACOUT
GND
EN
PWM
DRIVE
ISL6207
BOOT
UGATE
PHASE
LGATE
3
FN9075.8
December 2, 2005
ISL6207
Absolute Maximum Ratings
Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
EN
, V
PWM
) . . . . . . . . . . . . . . . -0.3V to V
CC
+ 0.3V
BOOT Voltage (V
BOOT
). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V
BOOT to PHASE Voltage (V
BOOT-PHASE
) . . . . . . . . . . . -0.3V to 7V
PHASE Voltage
. . . . . . . . . . . . . GND - 0.3V (DC) to V
BOOT
+ 0.3V
. . . . . . . . . GND - 5V (<100ns Pulse Width, 10µJ) to V
BOOT
+ 0.3V
UGATE Voltage . . . . . . . . . . V
PHASE
- 0.3V (DC) to V
BOOT
+ 0.3V
. . . . . . .V
PHASE
- 4V (<200ns Pulse Width, 20µJ) to V
BOOT
+ 0.3V
LGATE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to V
VCC
+ 0.3V
. . . . . . . . . . . GND - 2V (<100ns Pulse Width, 4µJ) to V
VCC
+ 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 125°C
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
SOIC Package (Note 2) . . . . . . . . . . . .
110
N/A
QFN Package (Notes 3, 4). . . . . . . . . .
95
36
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10°C to 100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Bias Supply Current
BOOTSTRAP DIODE
Forward Voltage
PWM INPUT
Input Current
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
I
VCC
EN = LOW
PWM pin floating, V
VCC
= 5V
-
-
-
30
5.0
-
µA
µA
V
F
V
VCC
= 5V, forward bias current = 2mA
0.45
0.60
0.65
V
I
PWM
V
PWM
= 5V
V
PWM
= 0V
-
-
-
3.3
-
250
-250
-
-
300
-
-
1.7
-
-
µA
µA
V
V
ns
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Holdoff Time
EN INPUT
EN LOW Threshold
EN HIGH Threshold
SWITCHING TIME
UGATE Rise Time (Note 5)
LGATE Rise Time (Note 5)
UGATE Fall Time (Note 5)
LGATE Fall Time (Note 5)
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
t
RUGATE
t
RLGATE
t
FUGATE
t
FLGATE
t
PDLUGATE
t
PDLLGATE
V
VCC
= 5V
V
VCC
= 5V
V
VCC
= 5V, temperature = 25°C
1.0
-
-
-
-
2.0
V
V
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, Outputs Unloaded
V
VCC
= 5V, Outputs Unloaded
-
-
-
-
-
-
8
8
8
4
18
15
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
4
FN9075.8
December 2, 2005
ISL6207
Electrical Specifications
PARAMETER
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
OUTPUT
Upper Drive Source Resistance
R
UGATE
500mA Source Current
-10°C to 85°C
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
I
UGATE
R
UGATE
V
UGATE-PHASE
= 2.5V
500mA Sink Current
-10°C to 85°C
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
I
UGATE
R
LGATE
V
UGATE-PHASE
= 2.5V
500mA Source Current
-10°C to 85°C
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
I
LGATE
R
LGATE
V
LGATE
= 2.5V
500mA Sink Current
-10°C to 85°C
Lower Driver Sink Current (Note 5)
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
I
LGATE
V
LGATE
= 2.5V
-
-
-
-
-
-
-
-
-
-
-
-
1.0
1.0
2.0
1.0
1.0
2.0
1.0
1.0
2.0
0.4
0.4
4.0
2.5
2.2
-
2.5
2.2
-
2.5
2.2
-
1.0
0.8
-
Ω
Ω
A
Ω
Ω
A
Ω
Ω
A
Ω
Ω
A
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
t
PDHUGATE
t
PDHLGATE
TEST CONDITIONS
V
VCC
= 5V, Outputs Unloaded
V
VCC
= 5V, Outputs Unloaded
MIN
10
10
TYP
20
20
MAX
30
30
UNITS
ns
ns
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
EN (Pin 7 for SOIC-8, Pin 6 for QFN)
EN is the enable input pin. Connect this pin to HIGH to
enable, and LOW to disable, the IC. When disabled, the IC
draws less than 1µA bias current.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500kΩ resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
Description
Operation
Designed for speed, the ISL6207 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the LGATE
voltage and determines the upper gate delay time
[t
PDHUGATE
], based on how quickly the LGATE voltage drops
below 1V. This prevents both the lower and upper MOSFETs
from conducting simultaneously, or shoot-through. Once this
delay period is completed, the upper gate drive begins to rise
[t
RUGATE
], and the upper MOSFET turns on.
FN9075.8
December 2, 2005
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
5
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