74AHC30; 74AHCT30
8-input NAND gate
Rev. 4 — 22 July 2015
Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC30: CMOS level
For 74AHCT30: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74AHC30D
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
74AHC30GU12
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
XQFN12
plastic, extremely thin quad flat package; no leads;
12 terminals; body 1.70
2.00
0.50 mm
SOT1174-1
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
4. Marking
Table 2.
74AHC30D
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
74AHC30GU12
[1]
Marking codes
Marking
74AHC30D
74AHCT30D
AHC30
AHCT30
AHC30
AHT30
A3
[1]
Type number
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
2 of 17
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
6. Pinning information
6.1 Pinning
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad,
however if it is soldered the solder land should remain
floating or be connected to GND
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
Fig 6.
Pin configuration XQFN12 (SOT1174-1)
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
3 of 17
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
6.2 Pin description
Table 3.
Symbol
A
B
C
D
E
F
GND
Y
n.c.
n.c.
G
H
n.c.
V
CC
Pin description
Pin
SO14, TSSOP14 and DHVQFN14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XQFN12
1
2
3
4
5
7
6
8
-
-
9
10
11
12
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
not connected
data input
data input
not connected
supply voltage
Description
7. Functional description
Table 4.
Input
A
L
X
X
X
X
X
X
X
H
[1]
Function table
[1]
Output
B
X
L
X
X
X
X
X
X
H
C
X
X
L
X
X
X
X
X
H
D
X
X
X
L
X
X
X
X
H
E
X
X
X
X
L
X
X
X
H
F
X
X
X
X
X
L
X
X
H
G
X
X
X
X
X
X
L
X
H
H
X
X
X
X
X
X
X
L
H
Y
H
H
H
H
H
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
4 of 17
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14, TSSOP14 and DHVQFN14
XQFN12
[1]
[2]
[2]
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
250
Unit
V
V
mA
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V
V
O
<0.5 V or V
O
> V
CC
+ 0.5 V
V
O
=0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C,
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
C,
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
C,
the value of P
tot
derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
Min
2.0
0
0
40
-
-
74AHC30
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Min
4.5
0
0
40
-
-
74AHCT30
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
C
ns/V
ns/V
Unit
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
5 of 17
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