74VCXHQ163245
16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL
TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL
I
I
I
uc
d
)
ro
(s
P
ct
te
du
le
o
so
Pr
b
e
O
et
) -
ol
(s
bs
ct
O
u
-
od
s)
r
(
P
ct
te
du
le
o
so
Pr
b
e
O
t
le
so
b
O
I
I
I
I
I
I
I
I
I
HIGH SPEED: t
PD
=6.0ns (MAX.) at T
A
=85°C
V
CCA
= 3.0V V
CCB
= 2.3V; Bn to An
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 20µA(MAX.) at T
A
=85°C
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OHA
| = I
OLA
= 2.6mA MIN at
V
CCA
= 3.0V; V
CCB
= 1.65V or 2.3V
|I
OHB
| = I
OLB
= 6mA (MIN at
V
CCA
= 2.3V or 3.0V; V
CCB
= 1.65V)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SERIES RESISTOR ON A SIDE
LIMITED EMI NOISE: t
rA
≅
t
fA
≥
4ns at
C
L
=10pF
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 2.3V to 3.6V (1.2V Data
Retention)
V
CCB
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
BUS HOLD PROVIDED ON DATA INPUT
BOTH SIDE
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
TFBGA
µTFBGA
s)
t(
Table 1: Order Codes
PACKAGE
T&R
TSSOP48
TFBGA54
µTFBGA42
µTFBGA42
(*)
74VCXHQ163245TTR
74VCXHQ163245LBR
74VCXHQ163245TBR
74VCXHQ163245R-E
(*) Lead-Free Compliant.
isolated. The A-port interfaces with the 3V bus, the
B-port with the 2.5V and 1.8V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage. All floating
bus terminals during High Z State don’t need
external pull-up or pull-down resistor.
Figure 1: Logic Diagram
DESCRIPTION
The 74VCXHQ163245 is a dual supply low
voltage CMOS 16-BIT BUS TRANSCEIVER
fabricated with sub-micron silicon gate and
five-layer metal wiring C
2
MOS technology.
Designed for use as an interface between a 3.3V
bus and a 2.5V or 1.8V bus in a mixed 3.3V/
1.8V,3.3V/2.5V and 2.5V/1.8V supply systems, it
achieves high speed operation while maintaining
the CMOS low power dissipation and limited rise
and fall time (Low EMI).
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
nDIR inputs. The enable inputs nG can be used to
disable the device so that the buses are effectively
n = 1, 2
Rev. 3
January 2005
1/17
74VCXHQ163245
Table 4: Absolute Maximum Ratings
Symbol
V
CCA
V
CCB
V
I
V
I/OA
V
I/OB
V
I/OA
V
I/OB
I
IK
I
OK
I
OA
I
OB
Supply Voltage
Supply Voltage
DC Input Voltage
DC I/O Voltage (Output disabled)
DC I/O Voltage (Output disabled)
DC I/O Voltage
DC I/O Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Output Current
Parameter
Value
-0.5 to +4.6
-0.5 to +V
CCA
+0.5
-0.5 to +4.6
-0.5 to +4.6
-0.5 to +4.6
-0.5 to V
CCA
+ 0.5
-0.5 to V
CCB
+ 0.5
−
20
−
50
±
50
±
50
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
uc
d
)
ro
(s
P
ct
te
du
le
o
so
Pr
b
e
O
et
) -
ol
(s
bs
ct
O
u
-
od
s)
r
(
P
ct
te
du
le
o
so
Pr
b
e
O
t
le
so
b
O
I
CCA
I
CCB
P
d
T
L
T
stg
DC V
CC
or Ground Current
DC V
CC
or Ground Current
Power Dissipation
Storage Temperature
±
100
±
100
400
260
-65 to +150
Lead Temperature (10 sec)
s)
t(
mA
mA
°C
°C
mW
Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CCA
V
I
V
CCB
V
I/OA
V
I/OB
T
op
dt/dv
Parameter
Value
Unit
V
Supply Voltage
Supply Voltage
I/O Voltage
I/O Voltage
2.3 to 3.6
1.65 to V
CCA
0 to V
CCB
0 to V
CCA
0 to V
CCB
-40 to 85
0 to 10
V
V
V
V
Input Voltage (Dir, G)
Operating Temperature
°C
Input Rise and Fall Time (note 1)
ns/V
1) V
IN
from 0.8V to 2.0V at V
CC
=3.0V
4/17
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
