IS41C16105C
IS41LV16105C
1Mx16
16Mb DRAM WITH FAST PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
— 1,024 cycles/16 ms
• Refresh Mode:
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
— 5V ± 10% (IS41C16105C)
— 3.3V ± 10% (IS41LV16105C)
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range -40
o
C to 85
o
C
FEBRUARY 2012
DESCRIPTION
The
ISSI
IS41C16105C and IS41LV16105C are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns
per 16-bit word. It is asynchronous, as it does not require a
clock signal input to synchronize commands and I/O.
These features make the IS41C16105C and IS41LV16105C
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications that run without a clock to synchronize
with the DRAM.
The IS41C/LV16105C is packaged in a 42-pin 400-mil SOJ
and 400-mil 50/44-pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (t
rac
)
Max. CAS Access Time (t
cac
)
Min. Fast Page Mode Cycle Time (t
pc
)
Min. Read/Write Cycle Time (t
rc
)
-50
50
13
20
84
Unit
ns
ns
ns
ns
ns
Max. Column Address Access Time (t
aa
) 25
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
02/24/2012
1
IS41C16105C
IS41LV16105C
Functional Description
The IS41C/LV16105C is a CMOS DRAM optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 16 address bits. These are entered ten bits
(A0-A9) at a time. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter nine bits.
The IS41C/LV16105C has two CAS controls, LCAS and
UCAS. The LCAS and UCAS inputs internally generates
a
CAS
signal functioning in an identical manner to the
single CAS input on the other 1M x 16 DRAMs. The key
difference is that each CAS controls its corresponding I/O
tristate logic (in conjunction with OE and WE and RAS).
LCAS controls I/O0 through I/O7 and UCAS controls I/
O8 through I/O15.
The IS41C/LV16105C CAS function is determined by the
first CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41C16105C and IS41LV16105C both BYTE READ and
BYTE WRITE cycle capabilities.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the mem-
ory.
1. By clocking each of the 1,024 row addresses (A0 through
A9) with RAS at least once every t
ref
max. Any read,
write, read-modify-write or
RAS-only
cycle refreshes
the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
ras
time has expired. A new cycle
must not be initiated until the minimum precharge time
t
rp
, t
cp
has elapsed.
Power-On
During Power-On,
RAS, UCAS, LCAS,
and
WE
must
all track with V
dd
(HIGH) to avoid current surges,
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by t
ar
.
Data Out becomes valid only when t
rac
, t
aa
, t
cac
and t
oea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
02/24/2012
5
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