Si53108
DB800ZL 8-O
U T PUT
PCI
E
G
E N
3
BUFFER
/Z
ER O
D
ELAY
B
U F F E R
Features
Eight 0.7 V low-power, push-pull,
1.05 to 3.3 V power supply
HCSL-compatible PCIe Gen 3 voltage
outputs
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
Individual OE HW pins for each
compliant
output clock
100 MHz /133 MHz PLL
Gen 3 SRNS Compliant
operation, supports PCIe and
Industrial Temperature:
QPI
–40 to 85 °C
SMBus address is 0xD8
48-pin QFN
PLL or bypass mode
For higher output devices or
variations of this device, contact
Spread spectrum tolerable
Silicon Labs
Ordering Information:
See page 32.
Patents pending
Applications
Server
Storage
Datacenter
Enterprise Switches and Routers
Description
The Si53108 is a low-power, 8-output, differential clock buffer that meets
all of the performance requirements of the Intel DB800ZL specification.
The device is optimized for distributing reference clocks for Intel
®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
Rev. 1.2 12/15
Copyright © 2015 by Silicon Laboratories
Si53108
Si53108
Functional Block Diagram
OE_[7:0]
8
FB_OUT
SSC Compatible
PLL
CLK_IN
CLK_IN
DIF_[7:0]
100M_133
HBW_BYPASS_LBW
PWRGD / PWRDN
SDA
SCL
Control
Logic
2
Rev. 1.2
Si53108
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. OE and Output Enables (Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4. PWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6. SMBUS Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Rev. 1.2
3
Si53108
1. Electrical Specifications
Table 1. Absolute Maximum Ratings
Parameter
3.3 V Core Supply Voltage
1
3.3 V I/O Supply Voltage
1
3.3 V Input High Voltage
1,2
3.3 V Input Low Voltage
1
Storage Temperature
1
Input ESD protection
3
Symbol
V
DD
/V
DD_A
V
DD_IO
V
IH
V
IL
t
s
ESD
Min
—
—
—
−0.5
–65
2000
Max
4.6
4.6
4.6
—
150
—
Unit
V
V
V
V
°C
V
Notes:
1.
Consult manufacturer regarding extended operation in excess of normal DC operating parameters.
2.
Maximum V
IH
is not to exceed maximum V
DD
.
3.
Human body model.
Table 2. DC Operating Characteristics
V
DD_A
= 3.3 V±5%, V
DD
= 3.3 V±5%
Parameter
3.3 V Core Supply Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current
1
3.3 V Input High Voltage
2
3.3 V Input Low Voltage
2
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage
3
3.3 V Output Low Voltage
3
Input Capacitance
4
DIFF_IN Capacitance
Output pin Capacitance
Output Capacitance
4
Pin Inductance
Ambient Temperature
Symbol
VDD/VDD_A
V
IH
V
IL
I
IL
V
IH_FS
V
IL_FS
V
IL_Tri
V
IM_Tri
V
IH_Tri
V
OH
V
OL
C
IN
C
DIF_IN
C
OUT
C
OUT
L
PIN
T
A
Test Condition
3.3 V ±5%
VDD
0 < VIN < VDD
VDD
Min
3.135
2.0
VSS-0.3
–5
0.7
VSS–0.3
0
1.2
2.2
Max
3.465
VDD+0.3
0.8
+5
VDD+0.3
0.35
0.8
1.8
VDD
—
0.4
4.5
2.7
6
4.5
7
85
Unit
V
V
V
µA
V
V
V
V
V
V
V
pF
pF
pF
pF
nH
°C
I
OH
= –1 mA
I
OL
= 1 mA
2.4
—
2.5
1.5
2.5
—
No Airflow
–40
Notes:
1.
Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
2.
Internal voltage reference is to be used to guarantee V
IH
_FS and V
IL
_FS thresholds levels over full operating range.
3.
Signal edge is required to be monotonic when transitioning through this region.
4.
Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.2
Si53108
Table 3. Clock Input Parameters
T
A
= –40 to 85 °C; supply voltage V
DD
= 3.3 V ±5%
Parameter
Input Frequency
Symbol
F
IN
Test Condition
Bypass Mode
PLL Mode, 100 MHz
PLL Mode, 133.33 MHz
Min
33
90
120
600
V
SS
–300
300
300
0.4
–5
45
0
30
Typ
—
100
133.33
800
0
—
—
—
—
—
—
—
Max
150
110
147
1150
300
1000
1450
8
5
55
125
33
Unit
MHz
MHz
MHz
mV
mV
mV
Input High Voltage- CLK_IN V
IHDIF
Input Low Voltage- CLK_IN V
ILDIF
Input Common Mode
Voltage - CLK_IN
Input Amplitude- CLK_IN
Input Slew Rate- CLK_IN
Input Leakage Current
Input Duty Cycle
Input Jitter, Cycle-Cycle
Input SS Modulation Fre-
quency
V
COM
V
Swing
IDD
VDDAPD
I
IN
d
tin
J
DIFIN
f
MODIN
Differential inputs
single-ended measurement
Differential inputs
single-ended measurement
Common Mode Voltage Input
Peak to Peak
Measured differentially
V
IN
= V
DD
, V
IN
= GND
Measured from differential
waveform
Differential measurement
Triangle Wave Modulation
V/ns
A
%
ps
kHz
Table 4. Current Consumption
T
A
= –40 to 85 °C; supply voltage V
DD
= 3.3 V ±5%
Parameter
Operating Current
Symbol
IDD
VDD
IDD
VDDA
Test Condition
133 MHz, VDD Rail
133 MHz, VDDA + VDDR, PLL Mode
Power Down, VDD Rail
Power Down, VDDA Rail
Min
—
—
—
—
Typ
79
14
1
4
Max
90
20
1.5
8
Unit
mA
mA
mA
mA
Power Down Current IDD
VDDPD
IDD
VDDAPD
Rev. 1.2
5
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