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IS61QDB251236A-250M3L: 产品描述SRAM 18Mb 512Kx36 250MHz QUAD Sync SRAM; 产品类别存储; 文件大小591KB，共30页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/; 标准

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IS61QDB251236A-250M3L概述

SRAM 18Mb 512Kx36 250MHz QUAD Sync SRAM

IS61QDB251236A-250M3L规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	ISSI(芯成半导体)
产品种类 Product Category	SRAM
RoHS	Details
Memory Size	18 Mbit
Organization	512 k x 36
Maximum Clock Frequency	250 MHz
接口类型 Interface Type	Parallel
电源电压-最大 Supply Voltage - Max	1.9 V
电源电压-最小 Supply Voltage - Min	1.7 V
Supply Current - Max	1200 mA
最小工作温度 Minimum Operating Temperature	0 C
最大工作温度 Maximum Operating Temperature	+ 70 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	FBGA-165
系列 Packaging	Tray
Memory Type	Quad
Moisture Sensitive	Yes
工厂包装数量 Factory Pack Quantity	105

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IS61QDB21M18A

IS61QDB251236A

1Mx18, 512Kx36

18Mb QUAD (Burst 2) Synchronous SRAM

FEATURES



512Kx36 and 1Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data

valid window.

Separate independent read and write ports with

concurrent read and write operations.

Synchronous pipeline read with EARLY write

operation.

Double Data Rate (DDR) interface for read and

write input ports.

Fixed 2-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

Two output clocks (C and C#) for data output control.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

HSTL input and output levels.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x

user-supplied precision resistor.

NOVEMBER 2014

DESCRIPTION

The

and

are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround. The

rising edge of K clock initiates the read/write operation, and

all internal operations are self-timed. Refer to the

for a description of the

basic operations of these

SRAMs.

The input address bus operates at double data rate. The

following are registered internally on the rising edge of the K

clock:



Read address



Read enable



Write enable



Byte writes



Data-in for early writes

The following are registered on the rising edge of the K#

clock:



Write address



Byte writes



Data-in for second burst addresses



Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered half a cycle

earlier than the write address. The first data-in burst is

clocked at the same time as the write command signal, and

the second burst is timed to the following rising edge of the

K# clock.

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the second rising

edge of the C# clock (starting 1.5 cycles later after read

command). The data-outs from the second bursts are

updated with the third rising edge of the C clock. The K and

K# clocks are used to time the data-outs whenever the C and

C# clocks are tied high.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

IS61QDB21M18A

IS61QDB251236A

Ball Descriptions

Symbol

K, K#

Type

Input

Description

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

These balls cannot remain VREF level.

Input clock for output data. C and C# are used to clock out the READ data. They can be used

together to deskew the flight times of various devices on the board back to the controller. See

application example for further details.

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the

synchronous data outputs and can be used as a data valid indication. These signals run freely and

do not stop when Q tri-states.

DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in 1.0 read latency mode when the DLL is turned off. In this mode, the

device can be operated at a frequency of up to 167 MHz.

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K

and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of

individual signals.

The x18 device uses D0~D17. D18~D35 should be treated as NC pin.

The x36 device uses D0~D35.

Synchronous data outputs: Output data is synchronized to the respective C and C#, or to the

respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.

The x36 device uses Q0~Q35.

Synchronous write: When low, this input causes the address inputs to be registered and a WRITE

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous read: When low, this input causes the address inputs to be registered and a READ

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and #K for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating

Conditions for range.

Ground of the device

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this

ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance

mode. This ball cannot be connected directly to VSS or left unconnected.

IEEE1149.1 input pins for JTAG.

IEEE1149.1 output pins for JTAG.

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

C, C#

Input

CQ, CQ#

Output

Doff#

Input

D0 - Dn

Input

Q0 - Qn

Output

Input

reference

Power

Ground

REF

DDQ

TMS, TDI,

TCK

TDO

Input

Output

N/A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

IS61QDB21M18A

IS61QDB251236A

During a write, the byte writes independently control which byte of any of the four burst addresses is written (see

X18/X36 Write Truth Tables

and

Timing Reference Diagram for Truth Table).

Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM to adjust

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impedance matching is between 175Ω and 350Ω with V

DDQ

=1.5V. The RQ resistor should be placed less than two

inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ must never be

connected to V

PROGRAMMABLE IMPEDANCE AND POWER-UP REQUIREMENT

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values.

The final impedance value is achieved within 1024 clock cycles.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up

and must never change. Under this condition, K and K# will control the output timings.

Either clock pair must have both polarities switching and must never connect to V

REF

, as they are not differential

clocks.

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected

independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending

read and write transactions are always completed prior to deselecting the corresponding port.

Delay Locked Loop (DLL)

Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to

enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match

the clock frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with 1.0 cycle latency and a longer access time which is known in DDR-I or old QUAD

mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

IS61QDB251236A-250M3L相似产品对比

	IS61QDB251236A-250M3L	IS61QDB21M18A-250M3L	IS61QDB21M18A-250B4LI
描述	SRAM 18Mb 512Kx36 250MHz QUAD Sync SRAM	SRAM 18Mb 1Mx18 250Mhz QUAD Sync SRAM	SRAM 18Mb 1Mx18 250Mhz QUAD Sync SRAM
Product Attribute	Attribute Value	Attribute Value	Attribute Value
制造商 Manufacturer	ISSI(芯成半导体)	ISSI(芯成半导体)	ISSI(芯成半导体)
产品种类 Product Category	SRAM	SRAM	SRAM
RoHS	Details	Details	Details
Memory Size	18 Mbit	18 Mbit	18 Mbit
Organization	512 k x 36	1 M x 18	1 M x 18
Maximum Clock Frequency	250 MHz	250 MHz	250 MHz
接口类型 Interface Type	Parallel	Parallel	Parallel
电源电压-最大 Supply Voltage - Max	1.9 V	1.9 V	1.89 V
电源电压-最小 Supply Voltage - Min	1.7 V	1.7 V	1.71 V
Supply Current - Max	1200 mA	1150 mA	900 mA
最小工作温度 Minimum Operating Temperature	0 C	0 C	- 40 C
最大工作温度 Maximum Operating Temperature	+ 70 C	+ 70 C	+ 85 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	FBGA-165	FBGA-165	FBGA-165
系列 Packaging	Tray	Tray	Tray
Memory Type	Quad	DDR-II	QDR
Moisture Sensitive	Yes	Yes	Yes
工厂包装数量 Factory Pack Quantity	105	105	144
类型 Type	-	Quad	Synchronous

IS61QDB251236A-250M3L

IS61QDB251236A-250M3L在线购买

IS61QDB251236A-250M3L概述

IS61QDB251236A-250M3L规格参数

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