TSM3N100CP
Taiwan Semiconductor
N-Channel Power MOSFET
1000V, 2.5A, 6Ω
FEATURES
●
●
●
●
●
●
●
100% avalanche tested
Advanced planar process
Compliant to RoHS Directive 2011/65/EU and in
accordance to WEEE 2002/96/EC
Halogen-free according to IEC 61249-2-21
KEY PERFORMANCE PARAMETERS
PARAMETER
V
DS
R
DS(on)
(max)
Q
g
VALUE
1000
6
19
UNIT
V
Ω
nC
APPLICATIONS
AC/DC LED Lighting
Power Supply
Power Meter
TO-252 (DPAK)
Notes:
MSL 3 (Moisture Sensitivity Level) per J-STD-020
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
(Note 1)
SYMBOL
V
DS
V
GS
T
C
= 25°C
T
C
= 100°C
I
D
I
DM
P
DTOT
E
AS
I
AS
T
J
, T
STG
(Note 3)
(Note 3)
Limit
1000
±30
2.5
1.57
10
99
20
1.4
- 55 to +150
UNIT
V
V
A
A
W
mJ
A
°C
(Note 2)
Total Power Dissipation @ T
C
= 25°C
Single Pulse Avalanche Energy
Single Pulse Avalanche Current
Operating Junction and Storage Temperature Range
THERMAL PERFORMANCE
PARAMETER
Junction to Case Thermal Resistance
Junction to Ambient Thermal Resistance
SYMBOL
R
ӨJC
R
ӨJA
Limit
1.26
62
UNIT
°C/W
°C/W
Thermal Performance Note:
R
ӨJA
is the sum of the junction-to-case and case-to-ambient thermal resistances. The case-
thermal reference is defined at the solder mounting surface of the drain pins. R
ӨJA
is guaranteed by design while R
ӨCA
is
determined by the user’s board design. R
ӨJA
shown below for single device operation on FR-4 PCB in still air.
1
Version: A1606
TSM3N100CP
Taiwan Semiconductor
ELECTRICAL SPECIFICATIONS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
(Note 4)
CONDITIONS
V
GS
= 0V, I
D
= 250µA
V
DS
= V
GS
, I
D
= 250µA
V
GS
= ±30V, V
DS
= 0V
V
DS
= 1000V, V
GS
= 0V
V
GS
= 10V, I
D
= 1.25A
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
R
DS(on)
MIN
1000
3.5
--
--
--
TYP
--
4.5
--
--
5.6
MAX
--
5.5
±100
1
6
UNIT
V
V
nA
µA
Ω
Dynamic
(Note 5)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching
(Note 6)
Q
g
V
DS
= 800V, I
D
= 2.5A,
V
GS
= 10V
Q
gs
Q
gd
C
iss
V
DS
= 25V, V
GS
= 0V,
f = 1.0MHz
f = 1.0MHz, open drain
C
oss
C
rss
R
g
--
--
--
--
--
19
6
10
664
40
17
--
--
--
--
--
pF
Ω
nC
--
2.2
--
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Source-Drain Diode
Forward Voltage
(Note 4)
t
d(on)
V
DD
= 500V, R
G
= 25Ω,
I
D
= 1.25A, V
GS
= 10V
t
r
t
d(off)
t
f
--
--
--
--
45
25
70
28
--
--
--
--
ns
I
S
= 2.5A, V
GS
= 0V
V
R
= 100V, I
S
= 2.5A
dI
F
/dt = 100A/μs
V
SD
t
rr
Q
rr
--
--
--
--
378
1.62
1.4
--
--
V
ns
μC
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.
2.
3.
4.
5.
6.
Current limited by package
Pulse width limited by the maximum junction temperature
L = 20mH, I
AS
= 1.4A, V
DD
= 50V, R
G
= 25Ω, Starting T
J
= 25 C
Pulse test: PW ≤ 300µs, duty cycle ≤ 2%
For DESIGN AID ONLY, not subject to production testing.
Switching time is essentially independent of operating temperature.
o
ORDERING INFORMATION
PART NO.
TSM3N100CP ROG
PACKAGE
TO-252 (DPAK)
PACKING
2,500pcs / 13” Reel
2
Version: A1606
TSM3N100CP
Taiwan Semiconductor
CHARACTERISTICS CURVES
(T
C
= 25°C unless otherwise noted)
Output Characteristics
I
D
, Continuous Drain Current (A)
I
D
, Continuous Drain Current (A)
Transfer Characteristics
V
DS
, Drain to Source Voltage (V)
On-Resistance vs. Drain Current
V
GS
, Gate to Source Voltage (V)
V
GS
, Gate to Source Voltage (V)
Gate-Source Voltage vs. Gate Charge
R
DS(on)
, Drain-Source On-Resistance (Ω)
I
D
, Continuous Drain Current (A)
On-Resistance vs. Junction Temperature
Q
g
, Gate Charge (nC)
Source-Drain Diode Forward Current vs. Voltage
I
S
, Body Diode Forward Current (A)
R
DS(on)
, Drain-Source On-Resistance
(Normalized)
T
J
, Junction Temperature (°C)
V
SD
, Body Diode Forward Voltage (V)
3
Version: A1606
TSM3N100CP
Taiwan Semiconductor
CHARACTERISTICS CURVES
(T
C
= 25°C unless otherwise noted)
Capacitance vs. Drain-Source Voltage
BV
DSS
(Normalized)
Drain-Source Breakdown Voltage (V)
BV
DSS
vs. Junction Temperature
C, Capacitance (pF)
V
DS
, Drain to Source Voltage (V)
Maximum Safe Operating Area
I
D
, Continuous Drain Current (A)
T
J
, Junction Temperature (°C)
V
DS
, Drain to Source Voltage (V)
Continuous Drain Current (A)
Normalized Thermal Transient Impedance, Junction-to-Case (DPAK/IPAK)
10
1
Normalized Effective Transient
Thermal Impedance
SINGLE PULSE
R
ӨJC
=1.26˚C/W
10
0
10
-1
10
-2
Duty=0.5
Duty=0.2
Duty=0.1
Duty=0.05
Duty=0.02
Duty=0.01
Single pulse
10
-4
10
-3
Notes:
Duty = t
1
/ t
2
T
J
= T
C
+ P
DM
x Z
ӨJC
x R
ӨJC
10
-2
10
-1
10
-3 -5
10
Square Wave Pulse Duration (s)
4
Version: A1606
TSM3N100CP
Taiwan Semiconductor
PACKAGE OUTLINE DIMENSIONS
(Unit: Millimeters)
TO-252
SUGGESTED PAD LAYOUT
MARKING DIAGRAM
Y
= Year Code
M
= Month Code for Halogen Free Product
O
=Jan
P
=Feb
Q
=Mar
R
=Apr
S
=May
T
=Jun
U
=Jul
V
=Aug
W
=Sep
X
=Oct
Y
=Nov
Z
=Dec
L
= Lot Code (1~9, A~Z)
5
Version: A1606
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
