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Intel 845 Family Chipset-Mobile:
82845MP/82845MZ Chipset Memory
Controller Hub Mobile (MCH-M)
Datasheet
®
April 2002
Order Number: 250687-002
Intel 82845MP/82845MZ Chipset-Mobile (MCH-M)
R
®
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Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power
characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its
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this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel’s customers, and Intel’s customers
should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 845MP/845 MZ Memory Controller Hub (MCH-M) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © Intel Corporation 2002
2
Datasheet
250687-002
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Intel 82845MP/82845MZ Chipset-Mobile (MCH-M)
®
Contents
1.
Overview .................................................................................................................................... 14
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
2.
2.1.
2.2.
2.3.
2.4.
System Architecture ...................................................................................................... 15
Mobile Intel Pentium
4 Processor-M Host Interface .................................................... 15
1.2.1.
System Bus Error Checking ........................................................................ 16
System Memory Interface ............................................................................................. 16
AGP Interface................................................................................................................ 18
Hub Interface................................................................................................................. 18
MCH-M Clocking ........................................................................................................... 18
System Interrupts .......................................................................................................... 19
Host Interface Signals ................................................................................................... 21
DDR Interface................................................................................................................ 23
Hub Interface Signals .................................................................................................... 24
AGP Interface Signals ................................................................................................... 24
2.4.1.
AGP Addressing Signals ............................................................................. 24
2.4.2.
AGP Flow Control Signals ........................................................................... 25
2.4.3.
AGP Status Signals..................................................................................... 25
2.4.4.
AGP Strobes ............................................................................................... 26
2.4.5.
AGP/PCI Signals-Semantics ....................................................................... 27
Clocks, Reset, and Miscellaneous ................................................................................ 30
Voltage References, PLL Power ................................................................................... 31
Pin State Table .............................................................................................................. 31
Conceptual Overview of the Platform Configuration Structure...................................... 36
Standard PCI Bus Configuration Mechanism................................................................ 36
Routing Configuration Accesses ................................................................................... 37
3.3.1.
PCI Bus #0 Configuration Mechanism ........................................................ 37
3.3.2.
Primary PCI and Downstream Configuration Mechanism........................... 37
3.3.3.
AGP Configuration Mechanism ................................................................... 38
MCH-M Register Introduction........................................................................................ 38
I/O Mapped Registers ................................................................................................... 39
3.5.1.
CONFIG_ADDRESS – Configuration Address Register............................. 39
3.5.2.
CONFIG_DATA - Configuration Data Register ........................................... 41
Memory Mapped Register Space .................................................................................. 42
3.6.1.
DRAMWIDTH—DRAM Width Register....................................................... 43
3.6.2.
DQCMDSTR – Strength Control Register for DQ and CMD Signal
Groups ........................................................................................................ 44
3.6.3.
CKESTR – Strength Control Register for CKE Signal Group ..................... 45
3.6.4.
CSBSTR – Strength Control Register for CS# Signal Group...................... 46
3.6.5.
CKSTR – Strength Control Register for CK Signal Group (CK / CK#)........ 47
3.6.6.
RCVENSTR – Strength Control Register for RCVENOUT# Signals........... 48
Host-Hub Interface Bridge Device Registers – Device #0............................................. 48
3.7.1.
VID – Vendor Identification Register – Device#0 ........................................ 51
3.7.2.
DID – Device Identification Register – Device#0......................................... 51
3.7.3.
PCICMD – PCI Command Register – Device #0 ........................................ 52
3.7.4.
PCISTS – PCI Status Register – Device #0................................................ 53
Datasheet
3
Signal Description ...................................................................................................................... 20
2.5.
2.6.
2.7.
3.
3.1.
3.2.
3.3.
Register Description................................................................................................................... 36
3.4.
3.5.
3.6.
3.7.
250687-002
Intel 82845MP/82845MZ Chipset-Mobile (MCH-M)
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®
3.8.
RID – Revision Identification Register – Device #0..................................... 54
SUBC – Sub-Class Code Register – Device #0.......................................... 54
BCC – Base Class Code Register – Device #0........................................... 54
MLT – Master Latency Timer Register – Device #0.................................... 55
HDR – Header Type Register – Device #0 ................................................. 55
APBASE – Aperture Base Configuration Register – Device #0 .................. 56
SVID – Subsystem Vendor ID – Device #0 ................................................. 57
SID – Subsystem ID – Device #0 ................................................................ 57
CAPPTR – Capabilities Pointer – Device #0............................................... 57
AGPM- AGP Miscellaneous Configuration.................................................. 58
DRB[0:7] – DRAM Row Boundary Registers – Device #0 .......................... 58
DRA[0:7] – DRAM Row Attribute Registers – Device #0 ............................ 59
DRT – DRAM Timing Register – Device #0 ................................................ 60
DRC – DRAM Controller Mode Register – Device #0 ................................. 61
DERRSYN – DRAM Error Syndrome Register ........................................... 63
EAP – Error Address Pointer Register – Device #0 .................................... 63
PAM[0:6] – Programmable Attribute Map Registers – Device #0 ............... 64
FDHC – Fixed DRAM Hole Control Register – Device #0........................... 68
SMRAM – System Management RAM Control Register – Device #0 ......... 69
ESMRAMC – Extended System Mgmt RAM Control Register
– Device #0 ................................................................................................. 70
3.7.25.
ACAPID – AGP Capability Identifier Register – Device #0.......................... 71
3.7.26.
AGPSTAT – AGP Status Register – Device #0 .......................................... 72
3.7.27.
AGPCMD – AGP Command Register – Device #0..................................... 73
3.7.28.
AGPCTRL – AGP Control Register............................................................. 74
3.7.29.
APSIZE – Aperture Size – Device #0 .......................................................... 75
3.7.30.
ATTBASE – Aperture Translation Table Base Register – Device #0.......... 76
3.7.31.
AMTT – AGP Interface Multi-Transaction Timer Register – Device #0 ...... 77
3.7.32.
LPTT – AGP Low Priority Transaction Timer Register – Device #0............ 78
3.7.33.
TOM – Top of Low Memory Register – Device #0 ...................................... 79
3.7.34.
MCH-MCFG – MCH-M Configuration Register – Device #0 ....................... 80
3.7.35.
ERRSTS – Error Status Register – Device #0 ............................................ 81
3.7.36.
ERRCMD – Error Command Register – Device #0 .................................... 82
3.7.37.
SMICMD – SMI Command Register – Device #0 ....................................... 83
3.7.38.
SCICMD – SCI Command Register – Device #0 ........................................ 83
3.7.39.
SKPD – Scratchpad Data – Device #0........................................................ 84
3.7.40.
CAPID – Product Specific Capability Identifier ............................................ 84
AGP Bridge Registers – Device #1 ............................................................................... 85
3.8.1.
VID1 – Vendor Identification Register – Device #1 ..................................... 87
3.8.2.
DID1 – Device Identification Register – Device #1...................................... 87
3.8.3.
PCICMD1 – PCI-PCI Command Register – Device #1............................... 88
3.8.4.
PCISTS1 – PCI-PCI Status Register – Device #1....................................... 89
3.8.5.
RID1 – Revision Identification Register – Device #1................................... 90
3.8.6.
SUBC1- Sub-Class Code Register – Device #1.......................................... 90
3.8.7.
BCC1 – Base Class Code Register – Device #1......................................... 91
3.8.8.
MLT1 – Master Latency Timer Register – Device #1.................................. 91
3.8.9.
HDR1 – Header Type Register – Device #1 ............................................... 91
3.8.10.
PBUSN1 – Primary Bus Number Register – Device #1 .............................. 92
3.8.11.
SBUSN1 – Secondary Bus Number Register – Device #1 ......................... 92
3.8.12.
SUBUSN1 – Subordinate Bus Number Register – Device #1 .................... 92
3.8.13.
SMLT1 – Secondary Master Latency Timer Register – Device #1 ............. 93
3.8.14.
IOBASE1 – I/O Base Address Register – Device #1 .................................. 94
3.8.15.
IOLIMIT1 – I/O Limit Address Register – Device #1 ................................... 94
3.8.16.
SSTS1 – Secondary PCI-PCI Status Register – Device #1 ........................ 95
Datasheet
250687-002
3.7.5.
3.7.6.
3.7.7.
3.7.8.
3.7.9.
3.7.10.
3.7.11.
3.7.12.
3.7.13.
3.7.14.
3.7.15.
3.7.16.
3.7.17.
3.7.18.
3.7.19.
3.7.20.
3.7.21.
3.7.22.
3.7.23.
3.7.24.
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Intel 82845MP/82845MZ Chipset-Mobile (MCH-M)
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3.8.17.
3.8.18.
3.8.19.
3.8.20.
3.8.21.
3.8.22.
3.8.23.
3.8.24.
4.
4.1.
MBASE1 – Memory Base Address Register – Device #1 ........................... 96
MLIMIT1 – Memory Limit Address Register – Device #1............................ 97
PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ... 98
PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .... 99
BCTRL1 – PCI-PCI Bridge Control Register – Device #1 ......................... 100
ERRCMD1 – Error Command Register – Device #1 ................................ 101
DWTMC – DRAM Write Thermal Management Control ........................... 102
DRTMC – DRAM Read Thermal Management Control ............................ 104
System Address Map ............................................................................................................... 105
Memory Address Ranges ............................................................................................ 105
4.1.1.
VGA and MDA Memory Space.................................................................. 106
4.1.2.
PAM Memory Spaces................................................................................ 107
4.1.3.
ISA Hole Memory Space ........................................................................... 108
4.1.4.
TSEG SMM Memory Space ...................................................................... 108
4.1.5.
System Bus Interrupt APIC Memory Space .............................................. 109
4.1.6.
High SMM Memory Space ........................................................................ 109
4.1.7.
AGP Aperture Space (Device #0 BAR) ..................................................... 109
4.1.8.
AGP Memory and Prefetchable Memory................................................... 109
4.1.9.
Hub Interface A Subtractive Decode ......................................................... 110
AGP Memory Address Ranges ................................................................................... 110
4.2.1.
AGP DRAM Graphics Aperture ................................................................. 110
System Management Mode (SMM) Memory Range ................................................... 111
4.3.1.
SMM Space Definition............................................................................... 111
4.3.2.
SMM Space Restrictions ........................................................................... 112
I/O Address Space ...................................................................................................... 112
MCH-M Decode Rules and Cross-Bridge Address Mapping ...................................... 112
4.5.1.
Decode Rules for the Hub Interface A ...................................................... 112
4.5.2.
AGP Interface Decode Rules .................................................................... 113
Host Interface Overview .............................................................................................. 114
5.1.1.
Dynamic Bus Inversion.............................................................................. 114
5.1.2.
System Bus Interrupt Delivery................................................................... 114
5.1.3.
Upstream Interrupt Messages................................................................... 115
System Memory Interface ........................................................................................... 115
5.2.1.
DDR Interface Overview............................................................................ 115
5.2.2.
Memory Organization and Configuration................................................... 116
5.2.2.1.
Configuration Mechanism for SO-DIMMs..................................... 116
5.2.2.1.1.
Memory Detection and Initialization............................ 116
5.2.2.1.2.
SMBus Configuration and Access of the Serial
Presence Detect Ports................................................ 116
5.2.2.1.3.
Memory Register Programming ................................. 116
5.2.3.
DRAM Performance Description ............................................................... 117
5.2.3.1.
Data Integrity (ECC) ..................................................................... 117
AGP Interface Overview.............................................................................................. 117
5.3.1.
AGP Target Operations............................................................................. 118
5.3.2.
AGP Transaction Ordering........................................................................ 119
5.3.3.
AGP Signal Levels .................................................................................... 119
5.3.4.
4x AGP Protocol........................................................................................ 119
5.3.5.
Fast Writes ................................................................................................ 119
5.3.6.
AGP FRAME# Transactions on AGP........................................................ 120
4.2.
4.3.
4.4.
4.5.
5.
Functional Description.............................................................................................................. 114
5.1.
5.2.
5.3.
250687-002
Datasheet
5
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