— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
25
R
XC18V00 Series In-System-Programmable
Configuration PROMs
Product Specification
DS026 (v6.0) August 5, 2015
0
Features
•
In-System Programmable 3.3V PROMs for
Configuration of Xilinx FPGAs
♦
♦
•
•
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes
♦
♦
Endurance of 20,000 Program/Erase Cycles
Program/Erase Over Full Industrial Voltage and
Temperature Range (–40
°
C to +85
°
C)
•
•
•
•
•
Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
•
•
•
•
IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA
Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE™ Foundation™
Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging
Description
Xilinx introduces the XC18V00 series of in-system
programmable configuration PROMs (Figure
1).
Devices in
this 3.3V family include a 4-megabit, a 2-megabit, a
1-megabit, and a 512-kilobit PROM that provide an easy-to-
use, cost-effective method for reprogramming and storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each
rising clock edge. The FPGA generates the appropriate
number of clock pulses to complete the configuration. When
the FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
X-Ref Target - Figure 1
When the FPGA is in Master SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM. When
the FPGA is in Slave Parallel or Slave SelectMAP mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After CE and OE are
enabled, data is available on the PROM’s DATA (D0-D7)
pins. New data is available a short access time after each
rising clock edge. The data is clocked into the FPGA on the
following rising edge of the CCLK. A free-running oscillator
can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output
to drive the CE input of the following device. The clock
inputs and the DATA outputs of all PROMs in this chain are
interconnected. All devices are compatible and can be
cascaded with other members of the family or with the
XC17V00 one-time programmable serial PROM family.
OE/RESET
CLK
CE
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
CEO
Memory
Address
Data
Serial
or
Parallel
Interface
D0 DATA
Serial or Parallel Mode
7
D[1:7]
Parallel Interface
CF
DS026_01_040204
Figure 1:
XC18V00 Series Block Diagram
© 1999–2008, 2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries.
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
1
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R
XC18V00 Series In-System-Programmable Configuration PROMs
Pinout and Pin Description
Table 1
provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1:
Pin Names and Descriptions
Pin
Name
D0
Boundary-
Scan Order
4
3
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Pin Description
D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
44-pin VQFP
40
44-pin
PLCC
2
20-pin
SOIC &
PLCC
1
D1
6
5
D2
2
1
D0-D7 are the output pins to provide parallel
data for configuring a Xilinx FPGA in Slave
Parallel/SelectMAP mode.
D1-D7 remain in high-Z state when the PROM
operates in serial mode.
D1-D7 can be left unconnected when the
PROM is used in serial mode.
29
35
16
42
4
2
D3
8
7
27
33
15
D4
24
23
9
15
7
(1)
D5
10
9
25
31
14
D6
17
16
14
20
9
D7
14
13
19
25
12
CLK
0
Each rising edge on the CLK input increments
the internal address counter if both CE is Low
and OE/RESET is High.
When Low, this input holds the address
counter reset and the DATA output is in a high-
Z state. This is a bidirectional open-drain pin
that is held Low while the PROM is reset.
Polarity is NOT programmable.
When CE is High, the device is put into low-
power standby mode, the address counter is
reset, and the DATA pins are put in a high-Z
state.
Allows JTAG CONFIG instruction to initiate
FPGA configuration without powering down
FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
43
5
3
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
CF
22
21
DATA OUT
OUTPUT
ENABLE
10
16
7
(1)
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
2
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R
XC18V00 Series In-System-Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Cont’d)
Pin
Name
CEO
Boundary-
Scan Order
12
11
Function
DATA OUT
OUTPUT
ENABLE
Pin Description
Chip Enable Output (CEO) is connected to the
CE input of the next PROM in the chain. This
output is Low when CE is Low and OE/RESET
input is High, AND the internal address counter
has been incremented beyond its Terminal
Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
44-pin VQFP
21
44-pin
PLCC
27
20-pin
SOIC &
PLCC
13
GND
TMS
MODE
SELECT
6, 18, 28 & 41
5
3, 12, 24 &
34
11
11
5
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the system if the pin is not driven.
Positive 3.3V supply voltage for internal logic.
Positive 3.3V or 2.5V supply voltage connected
to the input buffers
(2)
and output voltage
drivers.
No connects.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CCINT
V
CCO
17, 35 & 38
(3)
23, 41 &
44
(3)
18 & 20
(3)
19
8, 16, 26 & 36 14, 22, 32 &
42
1, 2, 4,
11, 12, 20, 22,
23, 24, 30, 32,
33, 34, 37, 39,
44
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
NC
Notes:
1.
2.
3.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF
→
D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES
0502x093h,
the input buffers are supplied by V
CCINT
.
For devices with IDCODES
0503x093h,
the following V
CCINT
pins are no-connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package, and pin 20 in 20-pin SOIC and 20-pin PLCC packages.
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
3
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R
XC18V00 Series In-System-Programmable Configuration PROMs
Pinout Diagrams
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
1
2
3
4
5
6
7
8
9
10
20
19
18
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
VCCO
VCCINT*
NC
VCCINT*
18
19
20
21
22
23
24
25
26
27
28
3
2
1
20
NC
OE/RESET
D6
CE
VCCO
VCCINT*
GND
D7
NC
CEO
NC
TDI
TMS
TCK
D4/CF*
OE/RESET
DS026_12_20051007
4
5
6
7
8
9
19
18
VCCO
CLK
D2
D0
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
7
8
9
10
11
12
13
14
15
16
17
PC44/PCG44
Top View
39
38
37
36
35
34
33
32
31
30
29
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
SO20/
SOG20
Top
View
17
16
15
14
13
12
11
6
5
4
3
2
1
44
43
42
41
40
OE/RESET
D6
CE
*See pin descriptions.
DS026_14_102005
VCCINT*
TDO
D1
D3
D5
*See pin descriptions.
PC20/
PCG20
Top View
10
11
12
D7
17
16
15
13
CEO
14
D6
CE
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
VCCO
VCCINT*
NC
GND
*See pin descriptions.
DS026_15_20051007
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VQ44/VQG44
Top View
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
NC
OE/RESET
D6
CE
VCCO
VCCINT*
GND
D7
NC
CEO
NC
12
13
14
15
16
17
18
19
20
21
22
*See pin descriptions.
DS026_13_20051007
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
4
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R
XC18V00 Series In-System-Programmable Configuration PROMs
Xilinx FPGAs and Compatible PROMs
Table 2
provides a list of Xilinx FPGAs and compatible PROMs.
Table 2:
Xilinx FPGAs and Compatible PROMs
Device
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
Table 2:
Xilinx FPGAs and Compatible PROMs
(Cont’d)
Device
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Configuration
Bits
1,305,376
3,006,496
4,485,408
8,214,560
11,589,920
15,868,192
19,021,344
26,098,976
34,292,768
470,048
732,576
1,726,880
2,767,520
4,089,504
5,667,488
7,501,472
10,505,120
15,673,248
21,865,376
29,081,504
559,200
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
630,048
863,840
1,442,016
1,875,648
2,693,440
3,430,400
XC18V00 Solution
XC18V02
XC18V04
XC18V04 +
XC18V512
2 of XC18V04
3 of XC18V04
4 of XC18V04
5 of XC18V04
6 of XC18V04 +
XC18V512
8 of XC18V04 +
XC18V512
XC18V512
XC18V01
XC18V02
XC18V04
XC18V04
XC18V04
+ XC18V02
2 of XC18V04
3 of XC18V04
4 of XC18V04
5 of XC18V04 +
XC18V02
7 of XC18V04
XC18V01
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
XC18V04
XC18V04 +
XC18V512
XC18V04 +
XC18V02
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
XC18V04
Configuration
Bits
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
197,696
336,768
559,200
781,216
1,040,096
1,335,840
630,048
863,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
439,264
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
XC18V00 Solution
XC18V04
2 of XC18V04
2 of XC18V04
2 of XC18V04
3 of XC18V04
4 of XC18V04
4 of XC18V04
XC18V512
XC18V512
XC18V01
XC18V01
XC18V01
XC18V02
XC18V01
XC18V01
XC18V02
XC18V02
XC18V02
XC18V04
XC18V04
XC18V512
XC18V01
XC18V02
XC18V04
XC18V04 +
XC18V01
2 of XC18V04
3 of XC18V04
3 of XC18V04 +
XC18V01
Capacity
Devices
XC18V04
XC18V02
XC18V01
XC18V512
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
5
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