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74F652 Transceivers/Registers
March 1988
Revised January 2004
74F652
Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with
D-type flip-flops, and control circuitry arranged for multi-
plexed transmission of data directly from the input bus or
from internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
74F652 non-inverting data path
Ordering Code:
Order Number
74F652SC
(Note 1)
74F652SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2004 Fairchild Semiconductor Corporation
DS009581
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74F652
Unit Loading/Fan Out
Pin Names
A
0
–A
7
, B
0
–B
7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/
3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
U.L.
HIGH/LOW
1.0/1.0
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
−
12 mA/64 mA (48 mA)
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
Function Table
Inputs
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
H
L
L
L
L
H
H
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Inputs/Outputs (Note 2)
A
0
thru A
7
Input
Input
Input
Output
Output
Input
Output
B
0
thru B
7
Input
Operating Mode
Isolation
Store A and B Data
Not Specified Store A, Hold B
Output
Input
Input
Output
Output
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
H
H
H
H
X
L
L
L
H
H
L
H or L H or L
H or L
H or L
X
X
X
H or L
X
X
X
X
X
X
X
X
X
X
X
L
H
H
X
X
X
X
X
X
L
H
X
X
H
Not Specified Input
H or L
H or L H or L
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Note 2:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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2
74F652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
Note A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA
L
L
X
X
SAB
X
SBA
L
OEAB OEBA CPAB CPBA
H
H
X
X
SAB
L
SBA
X
Note C: Storage
Note D: Transfer Storage
Data to A or B
OEAB OEBA CPAB CPBA
X
L
L
H
X
H
X
X
SAB
X
X
X
SBA
X
X
X
FIGURE 1.
OEAB OEBA CPAB CPBA
H
L
H or L H or L
SAB
H
SBA
X
3
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74F652
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
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