19-1210; Rev 3; 3/07
KIT
ATION
EVALU
BLE
AVAILA
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
______________________________Features
♦
Single +3.3V Supply
♦
622Mbps Serial to 77Mbps Parallel Conversion
♦
165mW Power
♦
Synchronization Input for Data Realignment and
Reframing (MAX3680)
♦
Differential 3.3V PECL Clock and Data Inputs
♦
TTL Data Outputs
_________________General Description
The MAX3680/MAX3680A deserializer is ideal for con-
verting 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data in ATM and SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts PECL serial clock and data inputs, and deliv-
ers TTL clock and data outputs. The MAX3680 also pro-
vides a TTL synchronization input that enables data
realignment and reframing.
The MAX3680/MAX3680A is available in the extended-
industrial temperature range (-40°C to +85°C), in a 28-
pin SSOP package.
MAX3680/MAX3680A
__________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross-Connects
Pin Configuration appears at end of data sheet.
________________Ordering Information
PART
MAX3680EAI
MAX3680EAI+
MAX3680AEAI
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
28 SSOP
28 SSOP
+Denotes
lead-free package.
___________________________________________________________________Typical Operating Circuit
V
CC
= +3.3V
V
CC
PD7
V
CC
= +3.3V
V
CC
= +3.3V
130Ω
PHOTODIODE
130Ω
SD+
MAX3680/
MAX3680A
PD6
PD5
OVERHEAD
TERMINATION
MAX3675
82Ω
LIMITING
AMP
DATA
AND
CLOCK
RECOVERY
130Ω
82Ω
SD-
PD4
PREAMP
100Ω
PD3
V
CC
= +3.3V
PD2
130Ω
SCLK+
SCLK-
PD0
82Ω
82Ω
PCLK
SYNC
GND
PD1
MAX3664
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z
0
= 50Ω.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
MAX3680/MAX3680A
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
V
CC
........................................................................-0.5V to +5V
PECL Inputs (SD+/-, SCLK+/-) ................-0.5V to (V
CC
+ 0.5V)
TTL Input (SYNC) ....................................-0.5V to (V
CC
+ 0.5V)
TTL Outputs (PCLK, PD_)........................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
SSOP (derate 9.52mW/°C above +85°C) .....................619mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
PECL INPUTS
(SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
IN
= V
IH(MAX)
V
IN
= V
IL(MAX)
Output sourcing = 400µA
Output sinking = 400µA
-10
-10
2.4
0
V
IN
= V
IH(MAX)
V
IN
= V
IL(MAX)
V
CC
- 1.16
V
CC
- 1.81
-10
-10
2.0
0.8
10
10
V
CC
0.44
V
CC
- 0.88
V
CC
- 1.48
10
10
V
V
µA
µA
V
V
µA
µA
V
V
SYMBOL
I
CC
CONDITIONS
TTL outputs = high
MIN
25
TYP
50
MAX
90
UNITS
mA
TTL INPUT AND OUTPUTS
(SYNC, PCLK, PD_) (Note 1)
Note 1:
The SYNC input is available only on the MAX3680.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= +25°C, unless otherwise noted.) (Note 2)
PARAMETER
Maximum Serial Clock Frequency
Serial Data Setup Time
Serial Data Hold Time
Parallel Clock to Data Output Delay
SYMBOL
f
SCLK
t
SU
t
H
t
CLK-Q
V
CC
= +3.3V, C
L
= 18pF
CONDITIONS
MIN
622
800
50
-200
500
2000
TYP
MAX
UNITS
MHz
ps
ps
ps
Note 2:
AC characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
__________________________________________Typical Operating Characteristics
(V
CC
= +3.0V to +3.6V, unless otherwise noted.)
MAX3680/MAX3680A
MAXIMUM SERIAL-CLOCK FREQUENCY
vs. TEMPERATURE
MAX3680-01
SERIAL DATA SETUP TIME
vs. TEMPERATURE
MAX3680-02
1.3
SERIAL CLOCK FREQUENCY (GHz)
400
SERIAL DATA-SETUP TIME (ps)
1.2
360
1.1
320
1.0
280
0.9
240
0.8
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
SERIAL DATA HOLD TIME
vs. TEMPERATURE
MAX3680-03
SUPPLY CURRENT
vs. TEMPERATURE
MAX3680-04
-100
70
60
SUPPLY CURRENT (mA)
50
40
30
20
10
V
CC
= +3.0V
V
CC
= +3.3V
V
CC
= +3.6V
SERIAL DATA-HOLD TIME (ps)
-160
-220
-280
-340
-400
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
MAX3680/MAX3680A
Pin Description
PIN
MAX3680
1, 2, 5, 8,
14, 18, 25
3
4
6
7
9, 11, 12,
16, 20, 23,
27
10
—
13
15, 17, 19,
21, 22, 24,
26, 28
MAX3680A
1, 2, 5, 8,
14, 18, 25
3
4
6
7
11, 12, 16,
20, 23, 27
—
9, 10
13
15, 17, 19,
21, 22, 24,
26, 28
V
CC
SD+
SD-
SCLK+
SCLK-
GND
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
Inverting PECL Serial Clock Input
Ground
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
No Connection
TTL Parallel Clock Output
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
NAME
FUNCTION
SYNC
N.C.
PCLK
PD0–PD7
Detailed Description
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
4
TTL
SD+
SD-
SCLK+
SCLK-
PECL
TTL
8-BIT
PARALLEL
OUTPUT
REGISTER
PECL
8-BIT
SHIFT
REGISTER
TTL
PD7
PD6
TTL
PD5
PD4
TTL
PD3
TTL
PD2
MAX3680/
MAX3680A
TTL
PD1
TTL
3-BIT
COUNTER
PD0
SYNC
TTL
TTL
PCLK
Figure 1. Functional Diagram
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
MAX3680/MAX3680A
SCLK*
SD*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
PCLK
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
D8-
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2a. Functional Timing Diagram—Normal Operation
_______________________________________________________________________________________
5
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