HCF40193B
PRESETTABLE UP/DOWN COUNTERS
(DUAL CLOCK WITH RESET) BINARY TYPE
s
s
s
s
s
s
s
s
s
s
INDIVIDUAL CLOCK LINES FOR COUNTING
UP OR COUNTING DOWN
SYNCHRONOUS HIGH-SPEED CARRY AND
BORROW PROPAGATION DELAYS FOR
CASCADING
ASYNCHRONOUS RESET AND PRESET
CAPABILITY
MEDIUM-SPEED OPERATION - f
CL
= 8MHz
(typ.) AT 10 V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF40193BEY
HCF40193BM1
DESCRIPTION
HCF40193B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40193B Presettable Binary Up/Down Counter
consists of 4 synchronously clocked, GATED "D"
type flip-flops connected as a counter. The inputs
consist of four individual jam lines, a PRESET
ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY
PIN CONNECTION
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and BORROW outputs for multiple-stage counting
schemes are provided. The counter is cleared so
that all outputs are in a low state by a high on the
RESET line. A RESET is accomplished
asynchronously with the clock. Each output is
individually programmable asynchronously with
the clock to the level on the corresponding jam
input when the PRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP
line is high. The CARRY and BORROW signals
are high when the counter counts up or down. The
CARRY signal goes low one-half clock cycle after
the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low
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HCF40193B
one-half clock cycle after the counter reaches its
minimum count in the count-down mode. The
cascading of multiple packages is easily
accomplished without the need for additional
external circuitry by tying the BORROW and
CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the following
package.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
3, 2, 6, 7
4
5
11
12
13
14
15, 1, 10, 9
8
16
SYMBOL
Q1 to Q4
CLOCK
DOWN
CLOCK UP
PRESET
ENABLE
CARRY
BORROW
RESET
J1 to J4
V
SS
V
DD
NAME AND FUNCTION
Flip-Flop Outputs
Clock Down Input
Clock Up Input
Preset Enable Input
Count Up (Carry)
Count Down (Borrow)
Reset Input
Data Input
Negative Supply Voltage
Positive Supply Voltage
FUNCTIONAL DIAGRAM
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嵌入式系统
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