The LC75863W is the 1/3 duty LCD display driver that can directly drive up to 75 segments and can control up to
four general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30
keys to reduce printed circuit board wiring.
Features
Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes can be controlled from serial data (up to 75 segments).
Sleep mode and all segments off functions that are controlled from serial data.
Segment output port/general-purpose output port function switching that is controlled from serial data.
Serial data I/O supports CCB format communication with the system controller.
Direct display of display data without the use of a decoder provides high generality.
Independent VLCD for the LCD driver block (VLCD can be set to in the range VDD-0.5 to 6.0 volts.)
Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
RC oscillator circuit.
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
36
37
25
24
48
1
0.5
(0.75)
12
0.18
13
7.0
9.0
0.15
0.5
9.0
7.0
SQFP48(7X7)
1.7max
(1.5)
0.1
SQFP48(7X7)
CCB is a registered trademark of Semiconductor Components Industries, LLC.
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of this data sheet.
Semiconductor Components Industries, LLC, 2013
October, 2013
O2313HKPC B8-8715/D2001TN(OT) No.7135-1/25
LC75863W
Specifications
Absolute Maximum Ratings
at Ta = 25C, VSS = 0V
Parameter
Maximum supply voltage
Symbol
VDD max
VLCD max
VIN1
Input voltage
VIN2
VIN3
VOUT1
Output voltage
VOUT2
VOUT3
IOUT1
Output current
IOUT2
IOUT3
IOUT4
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Tstg
VDD
VLCD
CE, CL, DI
OSC, TEST
VLCD1, VLCD2, KI1 to KI5
DO
OSC
S1 to S25, COM1 to COM3, KS1 to KS6, P1 to P4
S1 to S25
COM1 to COM3
KS1 to KS6
P1 to P4
Ta = 85C
Conditions
Ratings
-0.3 to +7.0
V
-0.3 to +7.0
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
300
3
1
5
150
-40 to +85
-55 to +125
mW
C
C
mA
A
V
V
Unit
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges
at Ta = -40 to +85C, VSS = 0V
Ratings
Parameter
Symbol
VDD
VLCD
VLCD1
VLCD2
VIH1
VIH2
VIL
Rosc
Cosc
fosc
tds
tdh
tcp
tcs
tch
tH
tL
tr
tf
tdc
tdr
VDD
VLCD
VLCD1
VLCD2
CE, CL, DI
KI1 to KI5
CE, CL, DI, KI1 to KI5
OSC
OSC
OSC
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
CL
CE, CL, DI
CE, CL, DI
DO RPU = 4.7k, CL = 10pF *1
DO RPU = 4.7k, CL = 10pF *1
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
19
160
160
160
160
160
160
160
160
160
1.5
1.5
0.8VDD
0.6VDD
0
39
1000
38
76
Conditions
min
4.5
VDD-0.5
2/3VLCD
1/3VLCD
Supply voltage
typ
max
6.0
V
6.0
VLCD
VLCD
6.0
V
VDD
0.2VDD
V
k
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
V
unit
Input voltage
Input high level voltage
Input low level voltage
Recommended external resistance
Recommended external capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
DO output delay time
DO rise time
Note:
*1.
Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load
capacitance CL.
No.7135-2/25
LC75863W
Electrical Characteristics
for the Allowable Operating Ranges
Ratings
Parameter
Hysteresis
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
Pull-down resistance
Output off leakage current
Symbol
VH
VDET
IIH
IIL
VIF
RPD
IOFFH
VOH1
Output high level voltage
VOH2
VOH3
VOH4
VOL1
VOL2
Output low level voltage
VOL3
VOL4
VOL5
VMID1
VMID2
VMID3
VMID4
VMID5
Oscillator frequency
fosc
IDD1
IDD2
ILCD1
ILCD2
ILCD3
CE, CL, DI
CE, CL, DI
KI1 to KI5
KI1 to KI5
DO
KS1 to KS6
P1 to P4
S1 to S25
COM1 to COM3
KS1 to KS6
P1 to P4
S1 to S25
COM1 to COM3
DO
COM1 to COM3
S1 to S25
S1 to S25
COM1 to COM3
COM1 to COM3
OSC
VDD
VDD
VLCD
VLCD
VLCD
VDD = 5.0V
VO = 6.0V
IO = -500A
IO = -1mA
IO = -20A
IO = -100A
IO = 25A
IO = 1mA
IO = 20A
IO = 100A
IO = 1mA
1/2bias, IO =
100A
1/3bias, IO =
20A
1/3bias, IO =
20A
1/3bias, IO =
100A
1/3bias, IO =
100A
Rosc = 39k, Cosc = 1000pF
Sleep mode
VDD = 6.0V, output open,
fosc = 38kHz
Sleep mode
VLCD = 6.0V, output open,
1/2bias, fosc = 38kHz
VLCD = 6.0V, output open,
1/3bias, fosc = 38kHz
100
60
270
1/2VLCD
-1.0
2/3VLCD
-1.0
Output middle level voltage *2
1/3VLCD
-1.0
2/3VLCD
-1.0
1/3VLCD
-1.0
30.4
38
0.1
VLCD-1.0
VLCD-1.0
VLCD-1.0
VLCD-1.0
0.2
0.5
1.5
1.0
1.0
1.0
0.5
1/2VLCD
+1.0
2/3VLCD
+1.0
1/3VLCD
+1.0
2/3VLCD
+1.0
1/3VLCD
+1.0
45.6
100
540
5
200
120
A
kHz
V
V
VLCD-0.5
50
100
VI = 6.0V
VI = 0V
-5.0
0.05VDD
250
6.0
VLCD-0.2
V
Pin
CE, CL, DI,
KI1 to KI5
2.5
Conditions
min
typ
0.1VDD
3.0
3.5
5.0
max
V
V
A
A
V
k
A
unit
Current drain
Note:
*2
Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
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