Ordering number : ENA1935
LC87F2C64A
CMOS IC
64K-byte FROM and 2048-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F2C64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard
programmable), 2048-byte RAM, an on-chip debugger, sophisticated 16-bit timer/counter (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a calendar function (RTC), High-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO interface, two channels of UART interface
(full duplex), four 12bit-PWMs, a 12/8-bit 16-channel AD converter, a system clock frequency divider, an internal
reset function and a 28-source 10-vector interrupt feature.
Features
Flash
ROM
•
On-board-programmable with wide range (3.0 to 5.5V) of voltage source
•
Block-erasable in 128 byte units
•
Writable in 2-byte units
•
65536
×
8 bits
RAM
•
2048
×
9 bits
Minimum
Bus Cycle
•
83.3ns (12MHz at VDD=3.0V to 5.5V)
•
250ns (4MHz at VDD=2.4V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.0.21
O1911HKIM 20100216-S00003 No.A1935-1/28
LC87F2C64A
Minimum
Instruction Cycle Time
•
250ns (12MHz at VDD=3.0 to 5.5V)
•
750ns (4MHz at VDD=2.4 to 5.5V)
Temperature
Range
•
-30 to +70 degree Celsius
Ports
•
Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
•
Normal withstand voltage input port (Oscillator)
•
Reset pin
•
Power pins
71 (P0n, P1n, P2n, P30 to P34, P70 to P73, P8n, PAn,
PBn, PCn, Pen, XT2, CF2)
2 (XT1, CF1)
1 (RES)
6 (VSS1 to VSS3, VDD1 to VDD3)
Timers
•
Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with a 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from
the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as
PWM.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Base timer
1) The clock is selectable from the sub-clock (32.768kHz crystal oscillation/slow RC oscillation), system clock, and
prescaler output from timer 0.
2) Interrupts are programmable in 5 different time schemes.
•
Real time clock (RTC)
1) Used with a base timer, it can be used as a century + year + month + day + hour + minute + second counter.
2) Calendar counts up to December 31, 2799 with automatic leap-year calculation.
High-speed
Clock Counter
•
Count clocks with a maximum clock rate of 24MHz (when main clock is 12MHz)
•
Real-time output
No.A1935-2/28
LC87F2C64A
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baud rate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
4) HOLD/X’tal HOLD mode release function by receiving 1-byte (8-bit clock)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baud rates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 TCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART:
2 channels
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2-bit in continuous data transmission)
•
Built-in baudrate generator
Remote
Control Receiver Circuit
•
Noise rejection function on P73/INT3/T0IN pin (noise rejection filter’s time constant can be selected from 1,
32 or 128 tCYC.)
AD
Converter: 12 bits
×
16 channels
•
12 bits/8 bits AD converter resolution selectable
PWM:
4 channels
•
Multi frequency 12-bit PWM
Clock
Output Function
•
Output clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of the source clock of the system clock.
•
Output clock of the sub-clock.
Buzzer
Output
•
2kHz or 4kHz buzzer output can be generated using base timer.
Watchdog
Timer
•
Watchdog timer can generate interrupt or system reset.
•
Two types of watchdog timers are available:
(1) External RC watchdog timer
(2) Base timer watchdog timer
•
Watchdog timer with base timer can select only one period (1, 2, 4 or 8s) by the user option.
Once set the watchdog timer period and start the watchdog timer, the period is not changeable.
No.A1935-3/28
LC87F2C64A
Interrupts
•
28 sources, 10 vector addresses
(1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
(2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/INT4/T0L
INT3/INT5/Base timer0/ Base timer1/RTC
T0H
T1L/T1H
SIO0/UART1 receive/UART2 receive
SIO1/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, 5/SPI
Port0/T4/T5/PWM0, 1
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
•
IFLG (List of interrupt source flag function)
(1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the table above).
Subroutine
Stack Levels
•
1024 levels (Stack is allocated in RAM)
High-speed
Multiplication/Division Instructions
•
16 bits×8 bits
(5 tCYC execution time)
•
24 bits×16 bits
(12 tCYC execution time)
•
16 bits÷8 bits
(8 tCYC execution time)
•
24 bits÷16 bits
(12 tCYC execution time)
Oscillation
Circuits
•
On-chip fast RC oscillation circuit
: For system clock
•
On-chip slow RC oscillation circuit
: For system clock
•
CF oscillation circuit
: For system clock, with built in Rf
•
Crystal oscillation circuit
: For low-speed system clock
•
On-chip Frequency variable RC oscillation circuit
: For system clock
(1) Adjustable by ±4% (typical) step from selected center frequency
(2) Frequency measurable by referencing input signal from XT1
System
Clock Divider Function
•
Enables low power consumption operation
•
The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and 64μs
(at a main clock rate of 12MHz).
Internal
Reset Function
•
Power-on reset (POR) function
(1) POR reset is generated only at power-on.
(2) The POR release level can be selected through option configuration.
•
Low-voltage detection reset (LVD) function
(1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
(2) The use/no-use of the LVD function and the low voltage threshold level can be selected through option
configuration.
No.A1935-4/28
LC87F2C64A
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(1) Oscillation is not halted automatically.
(2) There are three ways of resetting the HALT mode.
1) Setting the reset pin to the lower level
2) System resetting by watchdog timer
3) Occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
(1) The CF, RC, crystal, and frequency variable RC oscillators automatically stop operation.
(2) There are five ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) System resetting by watchdog timer
3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level
4) Having an interrupt source established at port 0
5) Having an interrupt source established in SPI receiving 1-byte (8-bit clock)
•
X’'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
(2) The state of crystal oscillation established when the X’tal HOLD mode is entered is retained.
(3) Power-save mode is available for even lower current consumption.
(4) There are seven ways of resetting the X’tal HOLD mode.
1) Setting the reset pin to the low level
2) System resetting by watchdog timer
3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level
4) Having an interrupt source established at port0
5) Having an interrupt source established in the base timer circuit
6) Having an interrupt source established in the RTC
7) Having an interrupt source established in SPI receiving 1-byte (8-bit clock)
On-chip
Debugging Function (flash ROM version)
•
Supports software debugging with the test device installed on the target board.
Data
Security Function (flash ROM version)
•
Protects the program data stored in flash memory from unauthorized read or copy.
Note: The data security function does not necessarily provide an absolute data security.
Shipping
form
•
QFP80 (14×14): Lead-free type
•
TQFP80J (12×12): Lead-free type
Development
Tools
•
On-chip-debugger: TCB87 TypeB + LC87F2C64A
No.A1935-5/28
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