1:2 LVDS Output 1.8V Fanout Buffer
IDT8P34S1102I
Datasheet
Description
The IDT8P34S1102I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals.
The IDT8P34S1102I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and two low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the differential device input. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
Two low skew, low additive jitter LVDS output pairs
One differential clock input pair
Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz
Output skew: 3ps (typical)
Propagation delay: 400ps (maximum)
Low additive phase jitter, RMS; f
REF
= 156.25MHz,
12kHz- 20MHz: 42fs (typical)
Maximum device current consumption (I
EE
): 48mA
Full 1.8V supply voltage
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
V
DD
Pin Assignment
nQ1
nQ0
10
Q1
CLK
nCLK
Q0
nQ0
Q1
nQ1
12
11
nc
13
nc
14
nc
15
GND
16
Q0
9
8
V
REF
7
nCLK
6
CLK
5
VDD
4
V
REF
V
REF
1
2
3
GND
nc
nc
IDT8P34S1102I
16-lead VFQFN
3mm x 3mm x 0.925mm package body
1.7mm x 1.7mm ePad Size
NL Package
Top View
©2017 Integrated Device Technology, Inc.
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September 20, 2017
IDT8P34S1102I Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Note 1.
Number
1, 16
2, 3, 4, 13, 14, 15
5
6
7
Name
GND
nc
V
DD
CLK
nCLK
Power
Unused
Power
Input
Input
Pulldown
Pulldown/
Pullup
Type
Description
Power supply ground.
Do not connect.
Power supply pins.
Non-inverting differential clock/data input.
Inverting differential clock input.
Bias voltage reference. Provides an input bias voltage for the CLK, nCLK input
pair in AC-coupled applications. Refer to
Figures 2B and 2C
for applicable
AC-coupled input interfaces.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
8
9, 10
11, 12
1.
V
REF
Q0, nQ0
Q1, nQ1
Output
Output
Output
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
Note 1.
ESD - Charged Device Model
Note 1.
1.
According to JEDEC JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
©2017 Integrated Device Technology, Inc.
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September 20, 2017
IDT8P34S1102I Datasheet
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter
V
DD
I
DD
Power Supply Voltage
Power Supply Current
Q0 to Q1 terminated 100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
40
Maximum
1.89
48
Units
V
mA
Table 3B. Differential Input Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter
I
IH
I
IL
Input High Current
CLK, nCLK
CLK
Input Low Current
nCLK
V
REF
V
PP
V
CMR
1.
2.
3.
Reference Voltage for Input
Bias
Note 1.
Peak-to-Peak Voltage
Note3.
Common Mode Input Voltage
Note 2.
Note 3.
Test Conditions
V
IN
= V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
I
REF
= +100µA, V
DD
= 1.8V
V
DD
= 1.89V
Minimum
Typical
Maximum
150
Units
µA
µA
µA
-10
-150
0.9
0.2
0.9
1.30
1.0
V
DD
– (V
PP
/2)
V
V
V
V
REF
specification is applicable to the AC-coupled input interfaces shown in
Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
Table 3C. LVDS DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note 1.
Symbol Parameter
V
OD
V
OD
V
OS
V
OS
1.
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
Test Conditions
outputs loaded with 100
Minimum
247
Typical
Maximum
454
50
1.40
50
Units
mV
mV
V
mV
Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance)
©2017 Integrated Device Technology, Inc.
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September 20, 2017
IDT8P34S1102I Datasheet
AC Electrical Characteristics
Table 4. AC Electrical Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°
Note 1.
Symbol Parameter
f
REF
V/t
t
PD
tsk(o)
tsk(p)
tsk(pp)
Input Frequency CLK, nCLK
Input Edge Rate CLK, nCLK
Propagation Delay
Note 2. Note 3.
Output Skew
Note 4. Note 5.
Pulse Skew
Part-to-Part Skew
Note 6.
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
10% to 90%,
outputs loaded with 100
t
R
/ t
F
Output Rise/ Fall Time
20% to 80%,
outputs loaded with 100
115
260
ps
61
50
50
63
42
42
76
55
55
200
f
REF
= 100MHz
CLK, nCLK to any Qx, nQx
1.5
150
3
400
15
20
250
85
62
62
85
61
61
100
74
74
400
Test Conditions
Minimum
Typical
Maximum
1.2
Units
GHz
V/ns
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
1.
2.
3.
4.
5.
6.
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crossing point.
Input V
PP
is 0.4V.
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.
©2017 Integrated Device Technology, Inc.
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September 20, 2017
IDT8P34S1102I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 50fs (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel Oscillator as the input source.
©2017 Integrated Device Technology, Inc.
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September 20, 2017
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