IS42S32160C
16Mx32
512Mb SYNCHRONOUS DRAM
FEATURES:
•
•
•
•
•
•
•
•
Clock frequency: 166, 133 MHz
Fully synchronous operation
Internal pipelined architecture
Programmable Mode
– CAS# Latency: 2 or 3
– Burst Length: 1, 2, 4, 8, or full page
– Burst Type: interleaved or linear
Power supply V
dd
/V
ddq
+3.3V ± 0.3V
LVTTL interface
Auto Refresh and Self Refresh
Individual byte controlled by DQM0-3
AUGUST
2011
DESCRIPTION:
The ISSI's IS42S32160C is a 512Mb Synchronous
DRAM configured as a quad 4M x32 DRAM. It achieves
high-speed data transfer using a pipeline architecture
with a synchronous interface. All inputs and outputs sig-
nals are registered on the rising edge of the clock input,
CLK. The 512Mb SDRAM is internally configured by
stacking two 256MB, 16Mx16 devices. Each of the 4M
x32 banks is organized as 8192 rows by 512 columns
by 32 bits.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 2
CAS Latency = 3
Clk Frequency
CAS Latency = 2
CAS Latency = 3
Access Time from Clock
CAS Latency = 2
CAS Latency = 3
-6
10
6.0
100
166
6.5
5.4
-75
10
7.5
100
133
6.5
6
Unit
ns
ns
MHz
MHz
ns
ns
OPTIONS:
•
•
•
•
•
Die revision: C
Configuration(s): 16Mx32
Package(s): 90 Ball BGA (8x13mm)
Lead-free package available
Temperature Range: Commercial and Industrial
ADDRESS TABLE
Parameter
Configuration
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
16Mx32
4M x 32 x 4 banks
BA0, BA1
A10/AP
A0 – A12
A0 – A8
8192 / 64ms
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev.
C
07/20/11
1
IS42S32160C
PIN
DESCRIPTIONS
Symbol
Type
Description
CLK
CKE
Input
Input
Clock:CLK
is driven by the system clock.All SDRAM input signals are sampled on the positive edge
of CLK.CLK also increments the internal burst counter and controls the output registers.
Clock Enable:CKE
activates(HIGH)and deactivates(LOW) the CLK signal.If CKE goes low syn-
chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.
Bank Select:BS0
and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge
command is being applied.
Address Inputs:A0-A12
are sampled during the BankActivate command (row address A0-A12) and
Read/Write command (column address A0-A8 with A10 defining Auto Precharge) to select one
location in the respective bank.During a Precharge command,A10 is sampled to determine if all
banks are to be precharged (A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
BS0,BS1 Input
A0-A12 Input
CS#
Input
Chip Select:CS#
enables (sampled LOW) and disables (sampled HIGH) the command decoder.All
commands are masked when CS# is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.
Row Address Strobe:The
RAS# signal defines the operation commands in conjunction with the
CAS# and WE# signals and is latched at the positive edges of CLK.When RAS# and CS# are as-
serted “LOW”and CAS# is asserted “HIGH,”either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE# is
asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.
Column Address Strobe:The
CAS# signal defines the operation commands in conjunction with the
RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held “HIGH”and
CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then, the Read or
Write command is selected by asserting WE# “LOW”or “HIGH.”
Write Enable:The
WE# signal defines the operation commands in conjunction with the RAS# and
CAS# signals and is latched at the positive edges of CLK.The WE# input is used to select the
BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:DQM0-DQM3
are byte specific, nonpersistent I/O buffer controls. The I/O
buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency) when DQM is
sampled HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1
masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
RAS#
Input
CAS#
Input
WE#
Input
DQM0-3 Input
DQ0-31 Input/
Data I/O:The
DQ0-31 input and output data are synchronized with the positive edge of CLK.
Output
The I/Os are byte-maskable during Reads and Writes.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
C
07/20/11
1
3
IS42S32160C
OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Truth table shows
the operation commands.
Truth Table
Command
BankActivate
BankPrecharge
PrechargeAll
Write
(1),(2)
State
Idle
(3)
Any
Any
Active
(3)
CKEn-1 CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
DQM
(6)
BS0,1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
A10 A12, A11
A9-0
Row address
L
H
L
H
L
H
X
X
Column
address
(A0 ~A8)
Column
address
(A0 ~A8)
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
Write and Auto Precharge Active
(3)
Read
Read and Autoprecharge
Mode Register
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Active
(3)
Active
(3)
Set Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
Clock Suspend Mode Entry Active
Power Down Mode Entry
Any
(5)
OP code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit Active
Power Down Mode Exit
Any
(PowerDown)
Data Write/Output Enable Active
Data Mask/Output Disable Active
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6. DQM0-3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
C
07/20/11
5
NXP MCU
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