Balanced Line Receiver ICs
THAT
1240, 1243, 1246
FEATURES
• High CMRR: typ. 90 dB at 60Hz
• Excellent audio performance
– Wide bandwidth: typ. >8.6 MHz
– High slew rate: typ. 12 V/μs
– Low distortion: typ. 0.0006% THD
– Low noise: typ. -104 dBu
• Low current: typ. 2 mA
• Several gains: 0 dB, ±3 dB, ±6 dB
• Industry Standard Pinout
• Current Shunt Monitors
APPLICATIONS
• Balanced Audio Line Receivers
• Instrumentation Amplifiers
• Differential Amplifiers
• Precision Summers
Description
The THAT 1240-series of precision differen-
tial amplifiers was designed primarily for use as
balanced line receivers for audio applications.
Gains of 0 dB, ±3 dB, and ±6 dB are available to
suit various applications requirements.
These devices are laser trimmed in wafer
form to obtain the precision resistor matching
needed for high CMR performance and precise
gain. Manufactured in THAT Corporation’s
proprietary complementary dielectric isolation
(DI) process, the THAT 1240-series provides the
sonic benefits of discrete designs with the
simplicity, reliability, matching, and small size of
a fully integrated solution.
All three versions of the part typically exhibit
90 dB of common-mode rejection. With 12 V/μs
slew
rate,
>8.6
MHz
bandwidth,
and
0.0006 % THD, these devices are sonically trans-
parent. Moreover, current consumption is
typically a low 2 mA. Both surface-mount and
DIP packages are available.
The THAT 1246 is pin-compatible with the
TI INA137 and Analog Devices SSM2143, while
the THAT 1240 is pin-compatible with the
INA134 and the SSM2141.
Vcc
Pin Name
Ref
DIP Pin
1
2
3
4
5
6
7
8
SO Pin
1
2
3
4
5
6
7
8
In-
R
1
R
2
Sense
In-
In+
Vee
Vout
R
3
In+
R
4
Ref
Sense
Vout
Vcc
NC
Table 1. 1240-series pin assignments
Vee
Part no.
THAT1240
THAT1243
THAT1246
Gain
0 dB
-3 dB
-6 dB
NC
R
1
, R
3
R
2
, R
4
Gain
0 dB
±3 dB
±6 dB
Plastic DIP
1240P08-U
1243P08-U
1246P08-U
Plastic SO
1240S08-U
1243S08-U
1246S08-U
Figure 1. THAT 1240-series equivalent circuit diagram
Table 2. Ordering information
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2015, THAT Corporation; Document 600035 Rev 05
Document 600035 Rev 05
Page 2 of 8
THAT 1240 Series
Balanced Line Receiver ICs
SPECIFICATIONS
1
Absolute Maximum Ratings
2,3
Supply Voltages (V
CC
- V
EE
)
Maximum In
-
or In
+
Voltage
Max/Min Ref or Sense Voltage
Maximum Output Voltage (V
OM
)
40V
-50V + V
CC
, 50V + V
EE
V
CC
+ 0.5V, V
EE
- 0.5V
V
CC
+ 0.5V, V
EE
- 0.5V
Storage Temperature Range (T
ST
)
Operating Temperature Range (T
OP
)
Output Short-Circuit Duration (t
SH
)
Junction Temperature (T
J
)
-40 to +125 ºC
0 to +85 ºC
Continuous
+125 ºC
Electrical Characteristics
2,4
Parameter
Supply Current
Supply Voltage
Input Voltage Range
Symbol
I
CC
V
CC
-V
EE
V
IN-DIFF
Differential (equal and opposite swing)
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
Common Mode
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
Differential
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
Common Mode
All versions
Common Mode Rejection Ratio
6
CMRR
Matched source impedances; V
CM
= ±10V
DC
60Hz
20kHz
Power Supply Rejection Ratio
6
Total Harmonic Distortion
Output Noise
PSRR
THD
e
OUT
±3V to ±18V; V
CC
= -V
EE
; all gains
70
70
—
—
90
90
85
90
—
—
—
—
dB
dB
dB
dB
—
—
—
—
18
21
24
18
—
—
—
—
kΩ
kΩ
kΩ
kΩ
Conditions
No signal
Min
—
7
—
—
—
—
—
—
Typ
2.0
—
21.5
24.4
27.5
27.5
29.1
31
Max
2.8
36
—
—
—
—
—
—
Units
mA
V
dBu
dBu
dBu
dBu
dBu
dBu
V
IN-CM
Input Impedance
5
Z
IN-DIFF
Z
IN-CM
V
IN_DIFF
= 10dBV, f = 1kHz, BW = 22kHz, R
L
= 2 kΩ
—
22 Hz to 22kHz bandwidth
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
—
—
—
7
0.0006
—
%
-104
-105
-106
12
—
—
—
—
dBu
dBu
dBu
V/μs
Slew Rate
SR
R
L
= 2kΩ; C
L
= 300 pF, all gains
1. All specifications are subject to change without notice.
2. Unless otherwise noted, T
A
=25ºC, V
CC
=+15V, V
EE
= -15V.
3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; the functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not impli ed. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
4. 0 dBu = 0.775 Vrms.
5. While specific resistor ratios are very closely trimmed, absolute resistance values can vary ±25% from the typical values show n. Input impedance is
monitored by lot sampling.
6. Defined with respect to differential gain.
7. Parameter guaranteed over the entire range of power supply and temperature.
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2015, THAT Corporation; All rights reserved.
THAT 1240 Series
Balanced Line Receiver ICs
Page 3 of 8
Document 600035 Rev 05
Electrical Characteristics (con’t)
2,4
Parameter
Small signal bandwidth
Symbol
BW
-3dB
Conditions
R
L
= 2kΩ; C
L
= 10 pF
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
R
L
= 2kΩ; C
L
= 300 pF
1240 (0dB gain)
1243 (-3dB gain)
1246 (-6dB gain)
f = 1 kHz
R
L
= 2kΩ
R
L
= 2kΩ
No signal
R
L
= 0
Ω
Min
—
—
—
—
—
—
-0.05
V
CC
-2.5
—
-7
—
—
Typ
8.6
12.2
18
10.3
11.8
13.4
0
V
CC
-2
V
EE
+2
—
±25
—
Max
—
—
—
—
—
—
+0.05
—
V
EE
+2.5
+7
—
300
Units
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
V
mV
mA
pF
Output Gain Error
Output Voltage Swing
G
ER-OUT
V
O+
V
O-
V
OFF
I
SC
C
L
Output Offset Voltage
Output Short Circuit Current
Capacitive Load
7
V
CC
In-
R
1
b
R
2
Sense
~
½v
IN(DIFF)
½v
IN(DIFF)
Vout
~
In+
R
3
R
a
R
Ref
L
4
C
L
V
IN(CM)
~
V
EE
Figure 2. THAT 1240 series test circuit
Theory of Operation
The THAT 1240-series ICs consist of high
performance opamps with integrated, laser-trimmed
resistors. These designs take full advantage of
THAT’s fully complementary dielectric isolation (DI)
process to deliver excellent performance with low
current consumption. The devices are simple to
apply in many applications.
ratio. Trimming is performed in two cycles, both
using dc inputs. First, gain is set by trimming the
R
1
/R
2
pair. Then, CMRR is set by trimming the other
pair (R
3
/R
4
). Generally, only one resistor of each pair
is trimmed (whichever needs to increase to meet the
required specification).
To achieve 90 dB CMRR, the R
3
/R
4
ratio is
trimmed to within ±0.005 % of the R
1
/R
2
ratio. Since
the resistors themselves are on the order of 10 kΩ
(see Figure 1 for actual values, which change with the
specific part), an increase of as little as 0.6
Ω
can
reduce the CMRR from over 90 dB to only 84 dB.
The better the starting CMRR, the more impact (in
dB) a given added resistance will have.
Resistor Trimming, Values, and CMRR
The 1240-series devices rely upon proprietary,
laser-trimmed, silicon-chromium (Si-Cr), thin-film,
integrated resistors to deliver the precise matching
required to achieve a 90 dB common mode rejection
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2015, THAT Corporation; All rights reserved.
Document 600035 Rev 05
Page 4 of 8
THAT 1240 Series
Balanced Line Receiver ICs
Therefore, to achieve this high CMRR in
practice, care should be taken to ensure that all
source impedances remain balanced. To accomplish
this, PCB traces carrying signal should be balanced
in length, connector resistance should be minimized,
and any input capacitance (including strays) should
be balanced between the + and - legs of the input
circuitry. Note that the additional contact resistance
of some sockets is sufficient to undo the effects of
precision trimming. Therefore, socketing the parts is
not recommended. THAT’s 1200-series InGenius®
input stages address many of these difficulties
through a patented method of increasing common-
mode input impedance.
A further consideration is that after trimming,
the two resistor divider ratios are tightly controlled,
but the actual value of any individual resistor is not.
In fact, two of the four resistors are normally left
without trimming. The initial tolerance of the resis-
tors is quite wide, so it is possible for any given resis-
tor to vary over a surprisingly wide range, Lot-to-lot
variations of up to ±30 % are to be expected.
in absolute value of any individual resistor, RF
bypassing through the addition of R-C networks at
the inputs (series resistor followed by a capacitor to
ground at each input) is not recommended. The
added resistors can interact with the internal ones in
unexpected ways. If some impedance for the
RF-bypass capacitor to work against is deemed
necessary, THAT recommends the use of a ferrite
bead or balun instead.
If it is necessary to ac-couple the inputs of the
1240-series parts, the coupling capacitors should be
sized to present negligible impedance at any frequen-
cies of interest for common mode rejection. Regard-
less of the type of coupling capacitor chosen,
variations in the values of the two capacitors,
working against the 1240-series input impedance
(itself subject to potential imbalances in absolute
value, even when trimmed for perfect ratio match),
can unbalance common mode input signals, convert-
ing them to balanced signals which will not be
rejected by the CMRR of the devices. For this reason,
THAT recommends dc-coupling the inputs of the
1240-series devices.
Input Considerations
The 1240-series devices are internally protected
against input overload via an unusual arrangement of
diodes connecting the + and - Input pins to the
power supply pins. The circuit of Figure 3 shows the
arrangement used for the R
3
/R
4
side; a similar one
applies to the other side. The zener diodes prevent
the protection network from conducting until an
input pin is raised at least 50 V above V
CC
or below
V
EE
. Thus, the protection networks protect the
devices without constraining the allowable signal
swing at the input pins. The reference (and sense)
pins are protected via more conventional reverse-
biased diodes which will conduct if these pins are
raised above V
CC
or below V
EE
.
Because the 1240-series devices are input
stages, their input pins are of necessity connected to
the outside world. This is likely to expose the parts
to ESD when cables are connected and disconnected.
Our testing indicates that the 1240-series devices will
typically withstand application of up to 1,000 volts
under the human body ESD model.
To reduce risk of damage from ESD, and to
prevent RF from reaching the devices, THAT recom-
mends the circuit of Figure 4. C
3
through C
5
should
be located close to the point where the input signal
comes into the chassis, preferably directly on the
connector. The unusual circuit design is intended to
minimize the unbalancing impact of differences in
the values of C
4
and C
5
by forcing the capacitance
from each input to chassis ground to depend primar-
ily on the value of C
3
. The circuit shown is approxi-
mately ten times less sensitive to mismatches
between C
4
and C
5
than the more conventional
approach, in which the junction of C
4
and C
5
is
grounded directly. An excellent discussion of input
stage grounding can be found in the June 1995 issue
of the Journal of the Audio Engineering Society,
Vol. 43, No. 6, in articles by Stephen Macatee, Bill
Whitlock, and others.
Note that, because of the tight matching of the
internal resistor ratios, coupled with the uncertainty
Input Voltage Limitations
When configured, respectively, for -3 dB and
-6 dB gain, the 1243 and 1246 devices are capable of
accepting input signals above the power supply rails.
This is because the internal opamp’s inputs connect
to the outside world only through the on-chip resis-
tors R
1
through R
4
at nodes a and b as shown in
Figure 2. Consider the following analysis.
Differential Input Signals
For differential signals (v
IN(DIFF)
), the limitation to
signal handling will be output clipping. The outputs
of all the devices typically clip at within 2V of the
supply rails. Therefore, maximum differential input
signal levels are directly related to the gain and
supply rails.
Common Mode Input Signals
For common-mode input signals, there is no
output signal. The limitation on common-mode
handling is the point at which the inputs are
overloaded. So, we must consider the inputs of the
opamp.
For common mode signals (v
in(CM)
), the common
mode input current splits to flow through both R
1
/R
2
and through R
3
/R
4
. Because vb is constrained to
follow va, we will consider only the voltage at node a.
The voltage at a can be calculated as:
v
a
=
v
IN(CM)
v
IN(CM)
=
v
a
R
4
R
3
+R
4
Again, solving for v
IN(CM)
,
R
3
+R
4
R
4
For the 1240, (R
3
+ R
4
) / R
4
= 2. For the 1243,
(R
3
+ R
4
) / R
4
= 2.4. For the 1246, (R
3
+ R
4
) / R
4
=3.
Furthermore, the same constraints apply to v
a
as in
the differential analysis.
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2015, THAT Corporation; All rights reserved.
THAT 1240 Series
Balanced Line Receiver ICs
Page 5 of 8
Document 600035 Rev 05
-
V
CC
must be kept under 125 ºC to maintain the devices’
specifications.
These devices are stable with up to 300 pF of
load capacitance.
V
CC
+
Power Supply Considerations
Ref
In+
R
3
R
4
V
EE
V
EE
The 1240-series parts are not particularly sensi-
tive to the power supply, but they do contain wide
bandwidth opamps. Accordingly, small local bypass
capacitors should be located within a few inches of
the supply pins on these parts, as shown in Figure 4.
Selecting a Gain Variation
The three different parts offer different gain
structures to suit different applications. The 1246 is
customarily configured for -6 dB gain, but by revers-
ing the resistor connections, can also be configured
for +6 dB. The 1243 is most often configured for
-3 dB gain, but can also be configured for +3 dB.
The choice of input gain is determined by the input
voltage range to be accommodated, and the power
supply voltages used within the circuit.
To minimize noise and maximize signal-to-noise
ratio, the input stage should be selected and config-
ured for the highest possible gain that will ensure
that maximum-level input signals will not clip the
input stage or succeeding stages. For example, with
±18 V supply rails, the 1240-series parts have a
maximum output signal swing of +23 dBu. In order
to accommodate +24 dBu input signals, the
maximum gain for the stage is -1 dB. With ±15 V
supply rails, the maximum output signal swing is
~+21.1 dBu; here, -3 dB is the maximum gain. In
each case, a 1243 configured for -3 dB gain is the
ideal choice. The 1240 (0dB gain only) will not
provide enough headroom at its output to support a
+24 dBu input signal. The 1246 (configured for
-6 dB gain) will increase noise, thus reducing
dynamic range, by attenuating the input signal more
than necessary to support a +24 dBu input.
In fact, for most professional audio applications,
THAT recommends the -3 dB input configuration
possible only with the 1243 in order to preserve
dynamic range within a reasonable range of power
supply voltages and external headroom limits.
Figure 3. Representative input protection circuit
Following the same reasoning as above, the
maximum common mode input signal for the 1240 is
(2V
CC
- 4) V, and the minimum is (2V
EE
+ 4) V. For
the 1243, these figures are (2.4V
CC
- 4.8) V, and
(2.4V
EE
+ 4.8) V. For the 1246, these figures are
(3V
CC
- 6) V, and (3V
EE
+ 6) V.
Therefore, for common-mode signals and ±15 V
rails, the 1240 will accept up to ~26 V in either
direction. As an ac signal, this is 52 V peak-peak,
18.4 V rms, or +27.5 dBu. With the same supply
rails, the 1243 will accept up to ~31 V in either
direction. As an ac signal, this is 62 V peak-peak,
21.9 V rms, or +29 dBu. With the same supply rails,
the 1246 will accept up to ~39 V in either direction.
As an ac signal, this is 78 V peak-peak, 27.6 V rms,
or +31 dBu.
Of course, in the real world, differential and
common-mode signals combine. The maximum
signal that can be accommodated will depend on the
superposition of both differential and common-mode
limitations.
Output Considerations
The 1240-series devices are typically capable of
supplying 25 mA into a short circuit. While they will
survive a short, power dissipation will rise dramati-
cally if the output is shorted. Junction temperature
V
CC
C2
In-
C4
470p
C5
470p
100n
2
In-
7
V
CC
7
U1
1240
9k
Sense
6
Vout
5
-In
2
In-
9k
V
CC
C3
47p
5
Sens
6
Out
Ref
V
EE
3
1
U1
In+
4
Out
Output
THAT1246/1243/1240
In+
C1
100n
V
EE
+In
3
In+
9k
V
EE
4
9k
Ref
1
Figure 4. RFI and supply bypassing
Figure 5. Zero dB line receiver
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2015, THAT Corporation; All rights reserved.
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