SMBus Interfaced Battery Charger with Internal FETs
ISL95871C
The ISL95871C is a highly integrated Lithium-ion battery charger
controller, programmable over the System Management Bus
(SMBus) with internal switching FETs. High efficiency is achieved
with a DC/DC synchronous-rectifier buck converter, equipped with
diode emulation for enhanced light load efficiency and system bus
boosting prevention. The ISL95871C charges one to four
Lithium-ion series cells, and delivers up to 8A charge current.
Integrated MOSFETs and bootstrap diode result in fewer
components and smaller implementation area. Low offset
current-sense amplifiers provide high accuracy with 10mΩ sense
resistors. The ISL95871C provides 0.5% battery voltage accuracy.
The ISL95871C also provides a digital output that indicates the
presence of the AC-adapter as well as an analog output which
indicates the adapter current within 4% accuracy.
Features
• Internal Synchronous Buck Output Stage Power FETs
• 0.5% Battery Voltage Accuracy
• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBus 2-Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
- Adapter Current (3% Accuracy)
- AC-Adapter Detection
• 11-Bit Battery Voltage Setting
• 6 Bit Charge Current/Adapter Current Setting
• 8A Maximum Battery Charger Current
• 11A Maximum Adapter Current
• +8V to +22V Adapter Voltage Range
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
• Tablet PCs
• Portable Equipment with Rechargeable Batteries
Related Literature
• See
AN1590,
ISL95871C Evaluation Board User Guide
9
8
CHARGE CURRENT (A)
7
6
5
4
3
2
1
0
1
2
5
3
4
6
CHARGE CURRENT (A)
7
8
0
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
150
4 CELL
3 CELL
2 CELL
1 CELL
100
95
90
EFFICIENCY (%)
85
80
75
70
65
60
1 CELL
2 CELL
3 CELL
4 CELL
FIGURE 1. EFFICIENCY vs CHARGE CURRENT AND BATTERY
VOLTAGE (EFFICIENCY DCIN = 20V)
FIGURE 2. DERATING CURVE WITH NATURAL AIR FLOW
(MEASURED ON 10cm x 10cm EVALUATION BOARD)
June 8, 2011
FN6856.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95871C
Pin Configuration
ISL95871C
(50 LD 5x7 QFN)
TOP VIEW
VDDSMB
VCOMP
ICOMP
43
VREF
42
41 AGND
40 ACIN
39 NC
AGND
51
38 CSIP
37 AGND
36 CSIN
35 VDD
34 BOOT
VDDP
52
DCIN3
UGATE
49
53
33 UGATE
32 UGATE
31 VIN
30 VIN
PHASE
54
PHASE7
VIN
55
29 VIN
28 VIN
27 VIN
26 VIN
17
PHASE
18
PHASE
19
PHASE
20
PHASE
21
NC
22
VIN
23
VIN
24
VIN
25
VIN
SCL
SDA
ICM
46
NC
50
AGND 1
ACOK 2
VFB 3
CSON 4
CSOP 5
DCIN 6
NC 7
AGND 8
VDDP 9
VDDP 10
PHASE 11
PGND 12
PGND 13
PGND 14
PGND 15
PGND 16
49
48
47
45
NC
44
Pin Descriptions
PIN NUMBER
1, 8, 37, 51
2
SYMBOL
AGND
ACOK
DESCRIPTION
Analog Ground. Connect directly to the backside paddle. Connect to PGND and the system ground plane under
the IC.
AC-Adapter Detection Output. This open drain output is high impedance when ACIN is greater than 3.2V. The
ACOK output remains low when the ISL95871C is powered down. Connect a 10k pull-up resistor from ACOK
to VDDSMB. Range: 0V to 5V.
Battery Voltage Remote Sense. Connect to the battery pack positive terminal.
Charge Current-Sense Negative Input. Range: zero to battery voltage.
Charge Current-Sense Positive Input. Range: zero to battery voltage.
Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to AGND. Range: zero to adapter voltage.
No Connection. Pins 7, 21, 39, 45 and 50 are not connected.
Linear Regulator Output. VDDP is the output of the 5.2V linear regulator supplied from DCIN. VDDP also
directly supplies the LFET gate driver and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from
VDDP to PGND. Range: zero to 5.3V.
Output inductor connection. Connected to the source of the internal high-side N-Channel MOSFET Source and
low-side N-Channel MOSFET Drain. Range: 1 diode drop below ground to 1 diode drop above adapter voltage.
Power Ground. Connect PGND to the source of the low side MOSFET and to the system ground plane.
3
4
5
6
7, 21, 39, 45, 50
9, 10, 52
VFB
CSON
CSOP
DCIN
NC
VDDP
11, 17, 18, 19, 20, 54
12, 13, 14, 15, 16
PHASE
PGND
2
FN6856.2
June 8, 2011
ISL95871C
Pin Descriptions
(Continued)
PIN NUMBER
22, 23, 24, 25, 26, 27,
28, 29, 30, 55
32, 33, 53
34
35
36
38
40
SYMBOL
VIN
UGATE
BOOT
VDD
CSIN
CSIP
ACIN
DESCRIPTION
Power input to the switching FETs connected to the drain of internal upper FET. A very low ESR capacitor should
be place from the VIN pins to the PGND pins. Range: Min battery voltage to adapter voltage.
Upper Gate of the internal power FET. A 4700pF cap must be placed between UGATE and PHASE. Range: 1
diode drop below ground to 5.3V above adapter voltage.
High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BOOT to PHASE.
Range: 1 diode drop below ground to 5.3V above adapter voltage.
Power input for internal analog circuits. Connect a 4.7Ω resistor from VDD to VDDP and a 1µF ceramic
capacitor from VDD to AGND. Range: 0V to 5.3V.
Input Current-Sense Negative Input. Range: battery voltage to adapter voltage.
Input Current-Sense Positive Input. Range: battery voltage to adapter voltage.
AC-Adapter Detection Input. Connect to a resistor divider from the AC-adapter output. Output switching is
disabled when ACIN is below it threshold. The divider should be designed to pull ACIN above its threshold when
the adapter voltage is above battery voltage. Range: 0V to 5V.
3.2V internal reference voltage. Place a 0.1µF ceramic capacitor from VREF to AGND pin close to the IC.
Compensation Point for the charging current and adapter current regulation Loop. Connect 0.01µF to AGND.
See the “Charge Current Control Loop” on page 21 for details of selecting the ICOMP capacitor. Range: 0V to
5.3V.
Compensation Point for the voltage regulation loop. Connect a resistor in series with a small ceramic capacitor
to AGND, typically 4.7kΩ in series with 0.01µF. See “Voltage Control Loop” on page 22 for details on selecting
VCOMP components. Range: 0V to 5V.
Input Current Monitor Output. ICM voltage equals 20 x (V
CSIP
- V
CSIN
). Range: 0V to 5V.
SMBus Data I/O. Open-drain Output. Connect an external pull-up resistor according to SMBus specifications.
Range: 0V to 5V.
SMBus Clock Input. Connect an external pull-up resistor according to SMBus specifications. Range: 0V to 5V.
SMBus interface Supply Voltage Input. Bypass with a 0.1µF capacitor to AGND. Range: 0V to 5V.
42
43
VREF
ICOMP
44
VCOMP
46
47
48
49
51, 52, 53, 54, 55
ICM
SDA
SCL
VDDSMB
Back Side Paddles 5 terminals on the back side of the package provide additional electrical and thermal connection to
ISL95871C AGND, VDDP, UGATE, PHASE and VIN. PHASE and VIN paddles are the lowest thermal resistance
from the switching MOSFETs and should relatively large areas of copper to have low thermal resistance from
the FETs to the PCB and the ambient air. The AGND paddle is the lowest thermal resistance from the control
IC and should be connected to a relatively large area of copper to have low thermal resistance from the FETs
to the PCB and the ambient air.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL95871CHRZ
NOTES:
1. Add “-T*” suffix for Tape and Reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL95871C.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISL 95871CHRZ
TEMP RANGE
(°C)
-10 to +100
PACKAGE
(Pb-Free)
50 Ld 5x7 QFN
PKG.
DWG. #
L50.5x7
3
FN6856.2
June 8, 2011
ISL95871C
11
6
SMBUS
6
DCIN
VDDP REG
VDDP
VDDSMB
SDA
SCL
VDDP
ICM
CSIP
CSIN
-
+
DACS
DACV
DACI
DACS
EN
REFERENCE
VREF
VREF
20X
-
GMS
+
MIN
CURRENT
BUFFER
20X
-
DACI
GMI
+
FEED
FORWARD
PULSE
WIDTH
MODULATOR VDDP
VDDP
+
-
ACOK
ACIN
ACOK
EN
VIN
CSOP
CSON
-
+
BOOT
ICOMP
MIN
VOLTAGE
BUFFER
VCOMP
VFB
500k
-
100k
DACV
+
GMV
UGATE
PHASE
PGND
GND
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
AC-ADAPTER
R
S1
TO SYSTEM
CSIP
AGND
ACIN
DCIN
CSIN
VIN
PHASE
R
S2
IN-RUSH
LIMIT
CIRCUIT
AGND
ISL95871C
BOOT
UGATE
CSOP
CSON
VFB
PGND
PGND
SMART
BATTERY
ICOMP
VCOMP
VDDP
R
VCOMP
VREF
SDA
SCL
C
ICOMP
C
VCOMP
VDD
AGND
ACOK
ICM
SDA
SCL
VDDSMB
AGND
PGND
FIGURE 4. TYPICAL APPLICATION CIRCUIT
4
HOST
FN6856.2
June 8, 2011
ISL95871C
Table of Contents
Absolute Maximum Ratings.............................................................. 6
Thermal Information .......................................................................... 6
模拟与混合信号
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