INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT374
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive
edge-trigger; 3-state
FEATURES
•
3-state non-inverting outputs for bus oriented
applications
•
8-bit positive, edge-triggered register
•
Common 3-state output enable input
•
Independent register and 3-state buffer operation
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT374 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT374
The 74HC/HCT374 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The “374” is functionally identical to the “534”, but has
non-inverting outputs.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
77
3.5
17
HCT
13
48
3.5
17
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
OE
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
NAME AND FUNCTION
74HC/HCT374
3-state output enable input (active LOW)
3-state flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
FUNCTION TABLE
OPERATING
MODES
load and read
register
load register and
disable outputs
Notes
INPUTS
OE
L
L
H
H
CP
↑
↑
↑
↑
D
n
l
h
l
h
74HC/HCT374
INTERNAL
FLIP-FLOPS
L
H
L
H
OUTPUTS
Q
0
to Q
7
L
H
Z
Z
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP
transition
Z = high impedance OFF-state
↑
= LOW-to-HIGH CP transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to
+125
max.
250
50
43
225
45
38
225
45
38
90
18
15
120
24
20
90
18
15
5
5
5
4.0
20
24
ns
74HC/HCT374
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
3-state output enable time
OE to Q
n
3-state output disable time
OE to Q
n
output transition time
50
18
14
41
15
12
50
18
14
14
5
4
80
16
14
60
12
10
5
5
5
6.0
30
35
19
7
6
14
5
4
−6
−2
−2
23
70
83
165
33
28
150
30
26
150
30
26
60
12
10
100
20
17
75
15
13
5
5
5
4.8
24
28
205
41
35
190
38
33
190
38
33
75
15
13
t
PZH
/ t
PZL
ns
Fig.7
t
PHZ
/ t
PLZ
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
set-up time
D
n
to CP
hold time
D
n
to CP
maximum clock pulse
frequency
ns
Fig.6
t
su
ns
Fig.8
t
h
ns
Fig.8
f
max
MHz
Fig.6
December 1990
5
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