Storage Temperature Range .............................-40ºC to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
FCLGA
Junction-to-Case Thermal Resistance (q
JC
) ...............10°C/W
Junction-to-Ambient Thermal Resistance
(q
JA
) (EIA/JESD51-2 standard)
...................................29°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Operating Conditions
PARAMETER
Supply Voltage
Operating Ambient
Temperature
Data Rate
Source Data Coding and
CID
Differential Source Diff Low-
Frequency Voltage
Source Rise/Fall Time
Source Common-Mode
Noise
Supply Noise
V
LAUNCH
DC balanced NRZ, 8B10B or
Scrambled; PRBS31
LF Baseline (without PE)
measured at source; source HF
pre-emphasis swing can be higher
Test source 10% to 90%
DC - 200MHz
DC - 1MHz
50
26
150
SYMBOL
V
CCR
,
V
CCT
,
V
CCP
T
A
CONDITIONS
MIN
2.312
-40
1
TYP
2.5
+25
MAX
2.75
+85
15
66
1200
UNITS
V
°C
Gbps
CID
mV
P-P
ps
mV
P-P
mV
P-P
Electrical Characteristics
(Typical values are at V
CCR
= V
CCT
= V
CCP
= 2.5V, T
A
= +25°C. See Figure
1
for typical supply filtering.) (Note 2)
PARAMETER
Supply Current
Supply Current During
Power-Down
SYMBOL
I
CCR
+
I
CCT
+
I
CCP
CONDITIONS
Total supply
current with all 8
channels enabled
TXAx[1:0] = 00
TXAx[1:0] = 11
MIN
TYP
420
511
4.8
MAX
550
610
UNITS
mA
mA
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Maxim Integrated │
2
MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
PARAMETER
Inrush Current
SYMBOL
(Typical values are at V
CCR
= V
CCT
= V
CCP
= 2.5V, T
A
= +25°C. See Figure
1
for typical supply filtering.) (Note 2)
CONDITIONS
Beyond steady-state supply current
with supply ramp-up time less than
200µs
Over-bit rate with EQ peaking
optimized for loss channel, in linear
range
EQx[3:0] = 1110
Peaking Gain
(Compensation at 7.5GHz,
relative to 100MHz,
100mV
P-P
Sine Wave Input)
EQx[3:0] = 1001
GN
P
EQx[3:0] = 0101
Variation around
typical
FGx[1:0] = 11
FGx[1:0] = 10
Flat Gain (100MHz, EQx[3:0]
= 1000, TXAx[1:0] = 10)
FGx[1:0] = 01
GN
F
FGx[1:0] = 00
Variation around
typical
TXAx[1:0] = 11
-1dB Compression Point
Output Swing (at 100MHz)
V
1dB_OUT
TXAx[1:0] = 10
TXAx[1:0] = 01
TXAx[1:0] = 00
-1dB Compression Point
Output Swing (Note 5) (at
7.5GHz)
TXAx[1:0] = 11
V
1dB_OUT
TXAx[1:0] = 10
TXAx[1:0] = 01
TXAx[1:0] = 00
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0] = 0000, Figure 3
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0] = 1010, Figure 3
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0] = 0000, Figure 3
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0] = 1010, Figure 3
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
-4.05
-3.32
-3.40
1000
1370
1280
1040
920
1000
940
700
600
0.6
0.5
0.8
1.0
1.97
mV
RMS
mV
RMS
mV
P-P
mV
P-P
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
-3.67
-1.61
-1.62
1.68
0.14
-1.36
-2.87
+0.95
+1.83
+2.86
dB
MIN
TYP
< 10
MAX
UNITS
%
Residual Deterministic Jitter
(Notes 3, 4)
DJ
RX
9
ps
P-P
18.5
15.7
13.2
+0.82
+1.96
+3.60
dB
Input-Referred Noise
V
NOISE
Output-Referred Noise
(Note 3)
V
NOISE
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Maxim Integrated │
3
MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
PARAMETER
HIGH SPEED I/O
Input Common-Mode Voltage
V
ICM
SYMBOL
(Typical values are at V
CCR
= V
CCT
= V
CCP
= 2.5V, T
A
= +25°C. See Figure
1
for typical supply filtering.) (Note 2)
CONDITIONS
MIN
TYP
MAX
2.05
DC differential resistance
Input Resistance
R
IN
AC common-mode (single-ended)
resistance
10MHz to 7.5GHz
1GHz to 7.5GHz
Differential
Common mode
100
50
> 16
> 10
100
50
3
2
4
S
22
V
Coup
10MHz to 7.5GHz
1GHz to 7.5GHz
Differential
Common Mode
> 13
>8
40
Ω
%
ps
ps
dB
dB
Ω
UNITS
V
Input Return Loss
S
11
dB
DC differential resistance
Output Resistance
Pulse Response Ringing
Intra-Pair Skew
Inter-Pair Skew
Output Return Loss
Channel Isolation
LVCMOS I/O
Input Logic-High Voltage
Input Logic-Low Voltage
Output Logic-High Voltage
Output Logic-Low Voltage
Open State Current Tolerance
V
IH
V
IL
V
OH
V
OL
H
IZ
V
IH(MIN)
< V
IN
< V
IH(MAX)
, all other
CMOS pins
V
IH(MIN)
< V
IN
< V
IH(MAX)
,
PGM_IN
Input Logic-Low Current
I
IL
V
IL(MIN)
< V
IN
< V
IL(MAX)
, all other
CMOS pins
V
IL(MIN)
< V
IN
< V
IL(MAX)
,
PGM_IN
-450
-18
At I
OH
= -200µA
At I
OL
= -200µA
0.7 x
V
CC
-0.3
V
CC
+
0.2
R
OUT
AC common mode (single-ended)
resistance
100MHz to 7.5GHz, Figure 4
(Note 6)
V
CC
+
0.3
0.3 x
V
CC
V
V
V
0.2
±5
±450
+120
V
mA
Input Logic-High Current
I
IH
mA
mA
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Maxim Integrated │
4
MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
PARAMETER
SYMBOL
(Typical values are at V
CCR
= V
CCT
= V
CCP
= 2.5V, T
A
= +25°C. See Figure
1
for typical supply filtering.) (Note 2)
CONDITIONS
MIN
TYP
MAX
0.3 x
V
CC
0.7 x
V
CC
200
10
±1
I
SINK
= 3mA
I
SINK
= 6mA
0.4
0.6
400
UNITS
I
2
C CHARACTERISTICS (SDA, SCL) (Note 7)
Low-Level Input Voltage
High-Level Input Voltage
Input Hysteresis
Input Capacitance
Input Leakage Current
Output Low Voltage SDA
SCLK Clock Frequency
V
IL
V
IH
V
HYS
C
IN
I
IN
V
OL
f
SCLK
V
V
mV
pF
mA
V
kHz
Note 2:
The MAX24101 is 100% production tested at T
A
= +25°C and T
A
= +85°C. Specification at T
A
= -40°C is guaranteed by
design or characterization, unless otherwise noted.
Note 3:
Guaranteed by design and characterization.
Note 4:
Measured with circuit board loss optimized for best DJ. Residual jitter is the difference in deterministic jitter between the
reference data source and device output. DJRESIDUAL = DJOUTPUT – DJSOURCE. The deterministic jitter at the output
of the transmission line must be from media induced loss. Measured at point D in
Figure 2. Test Patter: 66 Zeroes, 1010,
PRBS7, 66 ones, 0101 Inverted PRBS7.
Note 5:
The output voltage range in which a linear relationship between the input and output maintains less than or equal to 1dB
compression.
Note 6:
Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. The VNA detects
the signal at the output of the victim channel. All other inputs and outputs are terminated with 50Ω.
Note 7:
Refer to UM10204: I
2
C-bus specification and user manual, Rev. 03 – 19 June 2007.
IEC 61000-3-2 is the leading spec for PFC Harmonic limits EN61000-3-2 in Europe
BSEN 61000-3-2 in UK
JIC-C-61000-3-2 in Japan
GB 17625.1 in China
PF>0.7 for Residential ......
Warning: Only 16bit will be pushed to the stack. Use size specifier to avoid warning. C:\Documents and Settings\Administrator\桌面\UCOS_II\Port\Os_cpu_a.s43 216
用430F2418单片机 ......
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