32K x 32 CacheRAM™
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
Features
◆
◆
◆
◆
IDT71V432
◆
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
◆
◆
◆
◆
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW),
byte write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular
plastic thin quad flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
LBO
ADV
CE
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Binary
Counter
CLR
2
Burst
Logic
15
A
0
*
A
1
*
32K x 32
BIT
MEMORY
ARRAY
.
32
A
0
, A
1
15
2
A
2
–A
14
32
A
0
–A
14
GW
BWE
BW
1
15
Byte 1
Write Driver
Byte 2
Write Register
8
Byte 2
Write Driver
BW
2
Byte 3
Write Register
8
Byte 3
Write Driver
BW
3
Byte 4
Write Register
8
Byte 4
Write Driver
BW
4
8
OUTPUT
REGISTER
CE
CS
0
CS
1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OUTPUT
BUFFER
OE
32
I/O
0
–I/O
31
3104 drw 01
OCTOBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC-3104/08
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit
CacheRAM organized as 32K x 32 with full support of the
Pentium™ and PowerPC™ processor interfaces. The pipelined
burst architecture provides cost-effective 3-1-1-1 secondary
cache performance for processors up to 100 MHz.
The IDT71V432 CacheRAM contains write, data, address,
and control registers. Internal logic allows the CacheRAM to
generate a self-timed write based upon a decision which can be
left until the extreme end of the write cycle.
The burst mode feature offers the highest level of perfor-
mance to the system designer, as the IDT71V432 can provide
four cycles of data for a single address presented to the
CacheRAM. An internal burst address counter accepts the first
cycle address from the processor, initiating the access sequence.
The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of
output data will be available to the user on the next three rising
clock edges. The order of these three addresses will be defined
by the internal burst counter and the
LBO
input pin.
The IDT71V432 CacheRAM utilizes high-performance, high-
volume 3.3V CMOS process, and is packaged in a JEDEC
Standard 14mm x 20mm 100-pin thin plastic quad flatpack
(TQFP) for optimum board density in both desktop and notebook
applications.
Pin Description Summary
A
0
–A
14
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1,
BW
2,
BW
3,
BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
–I/O
31
V
DD
V
SS
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Ground
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
DC
DC
3104 tbl 01
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
6.42
2
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
–A
14
ADSC
Pin Function
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
Burst Address Advance
I/O
I
I
Active
N/A
LOW
Description
Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and
ADSC
Low or
ADSP
Low and
CE
Low.
Sy nchronous Ad dress Status from Cache Controller.
ADSC
is an active LOW
input that is used to load the address registers with new addresses.
ADSC
is
NOT GATED by
CE.
Synchronous Address Status from Processor.
ADSP
is an active LOW input that is
used to load the address registers with new addresses.
ADSP
is gated by
CE.
Synchronous Address Advance.
ADV
is an active LOW input that is used to
advance the internal burst counter, co ntrolling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs
BW
1
–BW
4
. If
BWE
is
LOW at the rising edge of CLK then
BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if
ADSP
is LOW at the rising edge of
CLK. If
ADSP
is HIGH and
BW
X
is LOW at the rising edge of CLK then data will
be written to the SRAM. If
BWE
is HIGH then the byte write inputs are blocked
and only
GW
can initiate a write cycle.
Synchronous byte write enables.
BW
1
controls I/O(7:0),
BW
2
controls I/O(15:8),
etc. Any active byte write causes all outputs to be disabled.
ADSP
LOW
disables all byte writes.
BW
1
–BW
4
must meet specified setup and hold times
with respect to CLK.
Synchronous chip enable.
CE
is used with CS
0
and
CS
1
to enable the
IDT71V432.
CE
also gates
ADSP.
This is the clock input to the IDT71V432. All timing referenc es for the device are
made with respect to this input.
Synchronous active HIGH chip select. CS
0
is used with
CE
and
CS
1
to enable
the chip.
Sy nchronous active LOW chip select.
CS
1
is used with
CE
and CS
0
to enable
the chip.
Synchronous global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK.
GW
supercedes individual byte write
enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
Asynchronous burst order sele ction DC input. When
LBO
is HIGH the Interleaved
(Intel) burst sequence is selected. When
LBO
is LOW the Linear (PowerPC) burst
sequence is selected.
LBO
is a static DC input and must not change state while
the device is operating.
Asynchronous output enable. When
OE
is LOW the data output drivers are
enabled on the I/O pins.
OE
is gated internally by a delay circuit driven by
CE,
CS
0
, and
CS
1
. In dual-bank mode, when the user is utilizing two banks of
IDT71V432 and toggling back and forth between them using
CE,
the internal
de lay circuit delays the
OE
activation of the data output drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode
CE,
CS
0
, and
CS
1
are all tied active and there is no output enable delay. When
OE
is
HIGH the I/O pins are in a high-impedence state.
3.3V power supply inputs.
Ground pins.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V432 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
3104 tbl 02
ADSP
ADV
I
I
LOW
LOW
BWE
Byte Write Enable
I
LOW
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
CE
CLK
CS
0
CS
1
Chip Enable
Clock
Chip Select 0
Chip Select 1
I
I
I
I
LOW
N/A
HIGH
LOW
GW
Global Write Enable
I
LOW
I/O
0
–I/O
31
LBO
Data Input/Output
Linear Burst Order
I/O
I
N/A
LOW
OE
Output Enable
I
LOW
V
DD
V
SS
ZZ
Power Supply
Ground
Sleep Mode
N/A
N/A
I
N/A
N/A
HIGH
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
(3)
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.6
–0.5 to V
DD
+0.5
0 to +70
–55 to +125
–55 to +125
1.0
50
Unit
V
V
o
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
0V
0V
V
DD
3.3V+10/-5%
3.3V+10/-5%
3104 tbl 03
C
C
C
W
mA
3104 tbl 05
Recommended DC Operating
Conditions
Symbol Parameter
V
DD
V
SS
V
IH
V
IH
V
IL
Supply Voltage
Ground
Input High Voltage — Inputs
Input High Voltage — I/O
Input Low Voltage
Min.
3.135
0
2.0
2.0
–0.5
(1)
Typ.
3.3
0
—
—
—
Max.
3.63
0
4.6
(2)
V
DD
+0.3
0.8
Unit
V
V
V
V
V
3104 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
NOTES:
1. V
IL
(min) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max) = 6.0V for pulse width less than t
CYC
/2, once per cycle.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
3104 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
4
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to V
DD
or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
模拟与混合信号
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